Features
TMS320C6454 Fixed-Point Digital Signal Processor
Description
1 ZTZ/GTZ BGA Package Bottom View
ZTZ/GTZ 697-PIN Ball Grid Array BGA Package Bottom View
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Functional Block Diagram
Functional Block Diagram
Temperature Unless Otherwise Noted
Contents
C6454
Device Characteristics
Characteristics of the C6454 Processor
Hardware Features
CPU DSP Core Description
Fixed-Point Digital Signal Processor
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Preview
C6454 Memory Map Summary
Memory Map Summary
Memory Block Description Block Size Bytes HEX Address Range
4FFF Ffff
2FFF Ffff
Ffff
3CFF Ffff
Boot Modes Supported
Boot Sequence
2 2nd-Level Bootloaders
Pin Map
Pin Assignments
C6454 Pin Map Bottom View Quadrant B
C6454 Pin Map Bottom View Quadrant C
C6454 Pin Map Bottom View Quadrant D
Signal Groups Description
SYSCLK4/GP1A
TMS320C6454 Fixed-Point Digital Signal Processor
TINPL1 TOUTL1
Gpio TOUTL0 TINPL0
ABE7 ABE6 ABE5 ABE4
ACE5A ACE4A
ACE3A
ACE2A
Clks Shared
HCNTL0/PSTOP HCNTL1/PDEVSEL HHWIL/PCLK HPI16 only
Hpia
CLKR1/GP0
Mdclk
Mdio
Rgmdio
Rgmdclk
HR/W/PCBE2 PINTA/GP14 HDS2/PCBE1
HHWIL/PCLK
Pidsel
PCBE3
Terminal Functions
Terminal Functions
Name
Type 1 IPD/IPU
Emifa 64-BIT Control Signals Common to ALL Types of Memory
Emifa 64-BIT BUS Arbitration
IPD/IPU
Emifa 64-BIT ASYNCHRONOUS/SYNCHRONOUS Memory Control
AEA14
Name Emifa 64-BIT Address
AEA1916
AEA15
AEA3
Signal Name
Type 1 IPD/IPU 2DESCRIPTION
AEA6
Name Emifa 64-BIT Data
IPD/IPU Description Name
DDR2 Memory Controller 32-BIT Address
IPD/IPU Description Name DDR2 Memory Controller 32-BIT Data
Timer
INTER-INTEGRATED Circuit I2C
Management Data INPUT/OUTPUT Mdio for Rgmii
Multichannel Buffered Serial Port 1 McBSP1
Multichannel Buffered Serial Port 0 McBSP0
Management Data INPUT/OUTPUT Mdio for MII/RMII/GMII
Reserved for Test
Ethernet MAC Emac Rgmii
RSV15
RSV12
RSV13
RSV14
RSV20
RSV17
RSV18
RSV19
Supply Voltage Pins
Supply Voltage Monitor Pins
IPD/IPU Description
E18
AB7
AA1 AA6
AC6 AC9
CV DD
AD5 AD7
AE6 AE8
AF1
GND
Ground Pins
F20 F22 F24 G11 G13 G15 G17 G19 G21 G23
M16 M18 M24 M26 M29 N13 N15 N17 N19 N23 P12 P14 P16 P18
AB6
AA2 AA7
AC7 AC8
AH1
AD6
AE4 AE7
AF2
Device and Development-Support Tool Nomenclature
Development
Development Support
Device Support
Device
Temperature Range
Prefix
Device Family
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AEA15
Device Configuration at Device Reset
C6454 Device Configuration Pins AEA190, ABA10, and Pcien
Configuration IPD PIN
AEA6
AEA14
AEA13
AEA8
Lower Upper
Peripheral Configuration at Device Reset
PCI
AEA6 PIN AEA8 PIN AEA14 PIN
MACSEL10 Peripheral Selection Emac
Peripheral Selection After Device Reset
Peripheral States
Unlock the PERCFG0 register by Using the Perlock register
Static Powerdown Reset Enable Progress Disabled Enabled
Device State Control Registers
Device State Control Registers
HEX Address Range Acronym Register Name
Lockval
Peripheral Lock Register Description
Lockval
Bit Field Value Description 310
Bit Field
Peripheral Configuration Register 0 Description
Description
Mode control for I2C
DDR2CTL Emifactl
Peripheral Configuration Register 1 Description
DDR2CTL
I2CSTAT
I2CSTAT Gpiostat TIMER1STAT TIMER0STAT Emacstat
Peripheral Status Registers Description
Hpistat
1715
Pcistat
Rmiirst
Emac Configuration Register Emaccfg Description
Emuctl
Emulator Buffer Powerdown Register Emubufpd Description
Pcieeai MACSEL1 MACSEL0
Device Status Register Description
Emifaen DDR2EN Pcien CFGGP2 CFGGP1 CFGGP0
Sysclkout MCBSP1EN PCI66
Lendian
Bit Field Value Description
Pcieeai
MACSEL10
Variant Part Number Manufacturer LSB
BOOTMODE30
Jtag ID Jtagid Register Description
Pullup/Pulldown Resistors
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Configuration Examples
Timers + Emac Gmii + Mdio
System Interconnect
Internal Buses, Bridges, and Switch Fabrics
Data Switch Fabric Connections
TMS320C6454
Switched Central Resource Block Diagram
SCR Connection Matrix
Configuration Switch Fabric
C64x+ Megamodule SCR Connection
Host Emac
Priority Allocation
ROM a
Memory Architecture
AET
Sram
TMS320C6454 L1P Memory Configurations
TMS320C6454 L2 Memory Configurations
AID0 Bit
Memory Protection
Bandwidth Management
Available Memory Page Protection Schemes
Reset Type Megamodule
Power-Down Control
Megamodule Resets
Megamodule Reset Global or Local
Revision
Megamodule Revision
Version Revision a
Version
Megamodule Interrupt Registers
C64x+ Megamodule Register Descriptions
Megamodule Revision Register
Megamodule Powerdown Control Registers
Megamodule Idma Registers
Megamodule Cache Configuration Registers
MAR168 Controls Emifa CE2 Range A800 0000 A8FF Ffff
Megamodule L1/L2 Memory Protection Registers
L2MPPA6
L2MPPA3
L2MPPA4
L2MPPA5
10. CPU Megamodule Bandwidth Management Registers
11. Device Configuration Registers Chip-Level Registers
HEX Address Range Acronym Register Name Comments
Cvdd
Recommended Operating Conditions
MIN NOM MAX Unit
Recommended Operating Conditions
TDO DVDD33 = MIN IOL = MAX
Parameter Test Conditions MIN TYP MAX Unit
OH = MAX
II DC
TDO
Tester Pin Electronics
1 3.3-V Signal Transition Levels
2 3.3-V Signal Transition Rates
Parameter Information
Timing Parameters and Board Routing Analysis
Power-Supply Decoupling
Recommended Clock and Control Signal Transition Behavior
Power Supplies
Power-Supply Sequencing
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EDMA3 Device-Specific Information
Enhanced Direct Memory Access EDMA3 Controller
C6454 EDMA3 Channel Synchronization Events1
EDMA3 Channel Synchronization Events
Edma Binary Event Name Event Description Channel
C6454 EDMA3 Channel Synchronization Events
EDMA3 Peripheral Register Descriptions
EDMA3 Channel Controller Registers
DCHMAP35
DCHMAP32
DCHMAP33
DCHMAP34
Emcrh
EMR
Emrh
Emcr
Q1E0 Event Queue 1 Entry Register
QSTAT3
QSTAT0
QSTAT1
QSTAT2
EDMA3 Parameter RAM1
EDMA3 Transfer Controller 0 Registers
EDMA3 Parameter RAM
EDMA3 Transfer Controller 1 Registers
EDMA3 Transfer Controller 2 Registers
109
EDMA3 Transfer Controller 3 Registers
111
Event Number Interrupt Event Interrupt Source
Interrupts
Interrupt Sources and Interrupt Controller
10. C6454 DSP Interrupts
TINTHI1
TINTLO0
TINTHI0
TINTLO1
Idmacmpa
L2DMPA
Idmabuserr
11. Timing Requirements for External Interrupts1 see Figure
External Interrupts Electrical Data/Timing
NMI
Type Initiator
Reset Controller
Power-on Reset POR Pin
12. Reset Types
Warm Reset Reset Pin
CPU Reset
System Reset
Reset Controller Register
Reset Priority
Reset Type Status Register Description
Parameter
Reset Electrical Data/Timing
14. Timing Requirements for Reset1 2 3see -8and Figure
720 1000
TMS320C6454
Power-Up Timing
CLKIN1 CLKIN2 POR
Resetstat
PLL1 and PLL1 Controller
Internal Clocks and Maximum Operating Frequencies
1 PLL1 Controller Device-Specific Information
1.2 PLL1 Controller Operating Modes
1.3 PLL1 Stabilization, Lock, and Reset Times
Clock Signal MIN MAX Unit
16. PLL1 Clock Frequency Ranges
MIN TYP
17. PLL1 Stabilization, Lock, and Reset Times
18. PLL1 Controller Registers Including Reset Controller
2 PLL1 Controller Memory Map
Pllpwrdn
3 PLL1 Controller Register Descriptions
3.1 PLL1 Control Register
Pllrst
20. PLL Multiplier Control Register Pllm Field Descriptions
PLL Multiplier Control Register
Preden
PLL Pre-Divider Control Register
Ratio
D4EN
PLL Controller Divider 4 Register
D5EN
PLL Controller Divider 5 Register
Goset
PLL Controller Command Register
Gostat
PLL Controller Status Register
PLL Controller Clock Align Control Register
SYS5 SYS4
Plldiv Ratio Change Status Register
SYS5
SYS5ON SYS4ON SYS3ON SYS2ON
Sysclk Status Register
X1 Bypass X20, x25, x30
29. Timing Requirements for CLKIN1 Devices1 2 3 see Figure
720 850 1000
PLL Modes Unit
PLL2 and PLL2 Controller
Pllref Pllen =
1 PLL2 Controller Device-Specific Information
31. PLL2 Clock Frequency Ranges
1.2 PLL2 Controller Operating Modes
HEX Address Range Acronym Description
2 PLL2 Controller Memory Map
3 PLL2 Controller Register Descriptions
32. PLL2 Controller Registers
D1EN
PLL Controller Divider 1 Register
PLL Controller Command Register
ALN1
SYS1
SYS1ON
39. Timing Requirements for CLKIN21 2 3 see Figure
4 PLL2 Controller Input Clock Electrical Data/Timing
1 DDR2 Memory Controller Device-Specific Information
DDR2 Memory Controller
3 DDR2 Memory Controller Electrical Data/Timing
2 DDR2 Memory Controller Peripheral Register Descriptions
40. DDR2 Memory Controller Registers
Emifa Device-Specific Information
External Memory Interface a Emifa
41. Emifa Registers
Emifa Peripheral Register Descriptions
42. Timing Requirements for Aeclkin for EMIFA1 2 see Figure
Emifa Electrical Data/Timing
Aeclkin
Aeclkin AECLKOUT1
720
720 850 1000UNIT
AAOE/ASOE a AAWE/ASWE a AR/W Aardy B Deasserted
Setup = Hold =
ACEx ABE70
ABA10 AED630 Read Data
ABA10 AED630
Strobe Setup = Extended Strobe
Aeclkout Aardya Asserted Deasserted
155
ASADS/ASREB AAOE/ASOEB AAWE/ASWEB
BE1 BE2 BE3 BE4
AEA190/ABA10
EA1 EA2 EA3 EA4
Write Latency =
Hold Holda
HOLD/HOLDA Timing
HHOLDAL-HOLDL Hold time, Hold low after Holda low
DSP Owns Bus
Busreq Timing
Delay time, Aeclkout high to Abusreq valid AECLKOUTx
11.1 I2C Device-Specific Information
11 I2C Peripheral
I2CXSR
I2COAR
SCL
I2CCLKH I2CSAR
51. I2C Registers
11.2 I2C Peripheral Register Descriptions
11.3 I2C Electrical Data/Timing
Standard Mode Fast Mode MIN MAX
Stop Start Repeated
SDA SCL
Unit MAX
Start Stop
Stop Start
54. HPI Control Registers
Host-Port Interface HPI Peripheral
HPI Device-Specific Information
HPI Peripheral Register Descriptions
HPI Electrical Data/Timing
See -56through Figure
HD150
HCS Has
HCNTL10
HR/W Hhwil Hstrobea
Hrdyb
HR/W Hhwil Hstrobe a
46. HPI16 Write Timing has Not Used, Tied High
47. HPI16 Write Timing has Used
HCS input HD310 output Hrdyb output
Has input HCNTL10 input HR/W input
49. HPI32 Read Timing has Used
Input HCS input
50. HPI32 Write Timing has Not Used, Tied High
Input HCS input HD310 input
51. HPI32 Write Timing has Used
Multichannel Buffered Serial Port McBSP
McBSP Device-Specific Information
58. McBSP 1 Registers
Product
McBSP Electrical Data/Timing
181
Clkx
Clks Clkr
Clks
Slave MIN MAX
Master Slave MIN MAX
Clkx FSX
Master Slave MIN
Hold time, DR valid after Clkx high + 36P
Setup time, DR valid before Clkx high 18P
186
Ethernet Bus
Ethernet MAC Emac
Interface Modes
Emac Device-Specific Information
Ball Number Device PIN Name
70. EMAC/MDIO Multiplexed Pins MII, RMII, and Gmii Modes
Rmii
Interface Mode Clocking
71. Ethernet MAC Emac Control Registers
Emac Peripheral Register Descriptions
RX6FREEBUFFER
Macconfig
Softreset
RX5FREEBUFFER
HEX Address Range Acronym
72. Emac Statistics Registers
74. Emac Descriptor Memory
73. Emac Control Module Registers
02C8 2000 02C8 3FFF Emac Descriptor Memory
Mtclk
Emac Electrical Data/Timing
MRXD3−MRXD0
Output 720 1000UNIT 1000 Mbps
1000 Mbps 100/10 Mbps
Mrclk Input MRXD7−MRXD4GMII only
NO.PARAMETER
MTXD3−MTXD0
MTXD7−MTXD0
Rmrefclk
Emac Rmii Electrical Data/Timing
MRXD1-MRXD0 Mcrsdv
Rmrefclk Input
Mrxer Inputs 720 1000
Output
Emac Rgmii Electrical Data/Timing
201
70. Emac Transmit Interface Timing Rgmii OperationAB
Mdio Device-Specific Information
Management Data Input/Output Mdio
Mdio Peripheral Register Descriptions 89. Mdio Registers
Mdio input
Delay time, Mdclk low to Mdio data output valid 100
Mdio output
92. Timer 0 Registers
Timers
Timers Device-Specific Information
Timers Peripheral Register Descriptions
94. Timing Requirements for Timer Inputs1 see Figure
Timers Electrical Data/Timing
TINPLx TOUTLx
PCI Device-Specific Information
96. Default Values for PCI Configuration Registers
Register Default Value
Peripheral Component Interconnect PCI
PCI Peripheral Register Descriptions
97. PCI Configuration Registers
98. PCI Back End Configuration Registers
99. DSP-toPCI Address Translation Registers
101. PCI External Memory Space
100. PCI Hook Configuration Registers
HEX Address Offset Acronym Register Name
4A7F Ffff
47FF Ffff
48FF Ffff
49FF Ffff
PCI Electrical Data/Timing
102. Gpio Registers
General-Purpose Input/Output Gpio
Gpio Device-Specific Information
Gpio Peripheral Register Descriptions
103. Timing Requirements for Gpio Inputs1 2 see Figure
Gpio Electrical Data/Timing
GPIx GPOx
105. Timing Requirements for Jtag Test Port see Figure
Ieee 1149.1 Jtag
Jtag Device-Specific Information
Ieee 1149.1 Jtag Compatibility Statement
AIR Flow
Thermal Resistance Characteristics S-PBGA Package ZTZ/GTZ
Thermal Data
Packaging Information
C6454 Revision History
Revision History
See ADDITIONS/MODIFICATIONS/DELETIONS
Changed -4title to EDMA3 Channel Controller Registers
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Revision History 221
Qty
Orderable Device Status Package
Eco Plan
MSL Peak Temp
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Important Notice
