TMS320C6454

Fixed-Point Digital Signal Processor

www.ti.com

SPRS311A –APRIL 2006 –REVISED DECEMBER 2006

Table 7-77. Switching Characteristics Over Recommended Operating Conditions for GMTCLK - GMII

Operation (see Figure 7-61)

NO.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

tc(GMTCLK)

Cycle time, GMTCLK

2

tw(GMTCLKH)

Pulse duration, GMTCLK high

3

tw(GMTCLKL)

Pulse duration, GMTCLK low

4

tt(GMTCLK)

Transition time, GMTCLK

 

 

 

 

1

 

 

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GMTCLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(Output)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

-720 -850

-1000UNIT 1000 Mbps

 

 

 

 

 

 

 

 

 

 

 

MIN

 

 

 

 

 

 

MAX

 

 

 

 

 

 

 

 

 

 

8

 

 

 

 

 

 

 

 

 

 

 

 

ns

 

 

 

 

 

 

 

 

 

2.8

 

 

 

 

 

 

 

 

 

 

 

 

ns

 

 

 

 

 

 

 

 

 

2.8

 

 

 

 

 

 

 

 

 

 

 

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

ns

 

 

 

 

 

 

 

 

 

 

 

4

 

 

 

 

 

 

 

 

 

 

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PRODUCT

Figure 7-61. GMTCLK Timing (EMAC – Transmit) [GMII Operation]

Table 7-78. Timing Requirements for EMAC MII and GMII Receive 10/100/1000 Mbit/s(1) (see Figure 7-62)

PREVIEW

NO.

1

tsu(MRXD-MRCLKH)

Setup time, receive selected signals valid before

MRCLK high

2

th(MRCLKH-MRXD)

Hold time, receive selected signals valid after

MRCLK high

 

-720

 

 

 

-850

 

 

 

-1000

 

UNIT

1000

Mbps

100/10 Mbps

 

MIN

MAX

MIN

MAX

2

 

8

ns

0

 

8

ns

(1)For MII, Receive selected signals include: MRXD[3:0], MRXDV, and MRXER. For GMII, Receive selected signals include: MRXD[7:0], MRXDV, and MRXER.

1

2

MRCLK (Input)

MRXD7−MRXD4(GMII only),

MRXD3−MRXD0,

MRXDV, MRXER (Inputs)

Figure 7-62. EMAC Receive Interface Timing [MII and GMII Operation]

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C64x+ Peripheral Information and Electrical Specifications

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Texas Instruments TMS320C6454 warranty Output 720 1000UNIT 1000 Mbps, Mbps 100/10 Mbps, Mrclk Input MRXD7−MRXD4GMII only