Texas Instruments TMS320C6454 guide

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TMS320C6454

Fixed-Point Digital Signal Processor

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SPRS311A –APRIL 2006 –REVISED DECEMBER 2006

7.7.3.8 PLL Controller Clock Align Control Register

The PLL controller clock align control register (ALNCTL) is shown in Figure 7-18and described in Table 7-26.

31					16
	Reserved
	R-0
15	5	4	3	2	0
Reserved		ALN5	ALN4		Reserved
R-0		R-1	R-1		R-1

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Figure 7-18. PLL Controller Clock Align Control Register (ALNCTL) [Hex Address: 029A 0140]

Table 7-26. PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions

Bit	Field	Value	Description
31:5	Reserved	0	Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
4:3	ALNn		SYSCLKn alignment. Do not change the default values of these fields.
		0	Do not align SYSCLKn to other SYSCLKs during GO operation. If SYSn in DCHANGE is set to 1,
			SYSCLKn switches to the new ratio immediately after the GOSET bit in PLLCMD is set.
		1	Align SYSCLKn to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set.
			The SYSCLKn ratio is set to the ratio programmed in the RATIO bit in PLLDIVn.
2:0	Reserved	0	Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

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C64x+ Peripheral Information and Electrical Specifications

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Texas Instruments TMS320C6454 warranty PLL Controller Clock Align Control Register

Contents

TMS320C6454 Fixed-Point Digital Signal Processor Features ZTZ/GTZ 697-PIN Ball Grid Array BGA Package Bottom View 1 ZTZ/GTZ BGA Package Bottom ViewDescription Submit Documentation Feedback Functional Block Diagram Functional Block Diagram Contents Temperature Unless Otherwise Noted Hardware Features Device CharacteristicsCharacteristics of the C6454 Processor C6454 Fixed-Point Digital Signal Processor CPU DSP Core Description Product Preview Preview Memory Block Description Block Size Bytes HEX Address Range Memory Map SummaryC6454 Memory Map Summary 3CFF Ffff 2FFF FfffFfff 4FFF Ffff Boot Sequence Boot Modes Supported 2 2nd-Level Bootloaders Pin Assignments Pin Map C6454 Pin Map Bottom View Quadrant B C6454 Pin Map Bottom View Quadrant C C6454 Pin Map Bottom View Quadrant D Signal Groups Description Gpio TOUTL0 TINPL0 TMS320C6454 Fixed-Point Digital Signal ProcessorTINPL1 TOUTL1 SYSCLK4/GP1A ACE2A ACE5A ACE4AACE3A ABE7 ABE6 ABE5 ABE4 CLKR1/GP0 HCNTL0/PSTOP HCNTL1/PDEVSEL HHWIL/PCLK HPI16 onlyHpia Clks Shared Rgmdclk MdioRgmdio Mdclk PCBE3 HHWIL/PCLKPidsel HR/W/PCBE2 PINTA/GP14 HDS2/PCBE1 Terminal Functions Terminal Functions Type 1 IPD/IPU Name Emifa 64-BIT Control Signals Common to ALL Types of Memory Emifa 64-BIT ASYNCHRONOUS/SYNCHRONOUS Memory Control IPD/IPUEmifa 64-BIT BUS Arbitration AEA15 Name Emifa 64-BIT AddressAEA1916 AEA14 AEA6 Signal NameType 1 IPD/IPU 2DESCRIPTION AEA3 Name Emifa 64-BIT Data IPD/IPU Description Name DDR2 Memory Controller 32-BIT Address INTER-INTEGRATED Circuit I2C TimerIPD/IPU Description Name DDR2 Memory Controller 32-BIT Data Management Data INPUT/OUTPUT Mdio for MII/RMII/GMII Multichannel Buffered Serial Port 1 McBSP1Multichannel Buffered Serial Port 0 McBSP0 Management Data INPUT/OUTPUT Mdio for Rgmii Ethernet MAC Emac Rgmii Reserved for Test RSV14 RSV12RSV13 RSV15 RSV19 RSV17RSV18 RSV20 IPD/IPU Description Supply Voltage Monitor PinsSupply Voltage Pins E18 AC6 AC9 AA1 AA6AB7 AF1 AD5 AD7AE6 AE8 CV DD Ground Pins GND F20 F22 F24 G11 G13 G15 G17 G19 G21 G23 M16 M18 M24 M26 M29 N13 N15 N17 N19 N23 P12 P14 P16 P18 AC7 AC8 AA2 AA7AB6 AF2 AD6AE4 AE7 AH1 Device Support DevelopmentDevelopment Support Device and Development-Support Tool Nomenclature Device Family Temperature RangePrefix Device Product Preview Configuration IPD PIN Device Configuration at Device ResetC6454 Device Configuration Pins AEA190, ABA10, and Pcien AEA15 AEA8 AEA14AEA13 AEA6 AEA6 PIN AEA8 PIN AEA14 PIN Peripheral Configuration at Device ResetPCI Lower Upper Peripheral States Peripheral Selection After Device ResetMACSEL10 Peripheral Selection Emac Static Powerdown Reset Enable Progress Disabled Enabled Unlock the PERCFG0 register by Using the Perlock register HEX Address Range Acronym Register Name Device State Control RegistersDevice State Control Registers Bit Field Value Description 310 Peripheral Lock Register DescriptionLockval Lockval Description Peripheral Configuration Register 0 DescriptionBit Field Mode control for I2C DDR2CTL Peripheral Configuration Register 1 DescriptionDDR2CTL Emifactl Hpistat I2CSTAT Gpiostat TIMER1STAT TIMER0STAT EmacstatPeripheral Status Registers Description I2CSTAT 1715 Pcistat Emac Configuration Register Emaccfg Description Rmiirst Emulator Buffer Powerdown Register Emubufpd Description Emuctl Sysclkout MCBSP1EN PCI66 Device Status Register DescriptionEmifaen DDR2EN Pcien CFGGP2 CFGGP1 CFGGP0 Pcieeai MACSEL1 MACSEL0 MACSEL10 Bit Field Value DescriptionPcieeai Lendian Pullup/Pulldown Resistors BOOTMODE30Jtag ID Jtagid Register Description Variant Part Number Manufacturer LSB Product Preview Configuration Examples Timers + Emac Gmii + Mdio Internal Buses, Bridges, and Switch Fabrics System Interconnect Data Switch Fabric Connections Switched Central Resource Block Diagram TMS320C6454 Configuration Switch Fabric SCR Connection Matrix C64x+ Megamodule SCR Connection Priority Allocation Host Emac Sram Memory ArchitectureAET ROM a TMS320C6454 L1P Memory Configurations TMS320C6454 L2 Memory Configurations Available Memory Page Protection Schemes Memory ProtectionBandwidth Management AID0 Bit Megamodule Reset Global or Local Power-Down ControlMegamodule Resets Reset Type Megamodule Version Megamodule RevisionVersion Revision a Revision C64x+ Megamodule Register Descriptions Megamodule Interrupt Registers Megamodule Idma Registers Megamodule Powerdown Control RegistersMegamodule Revision Register Megamodule Cache Configuration Registers MAR168 Controls Emifa CE2 Range A800 0000 A8FF Ffff Megamodule L1/L2 Memory Protection Registers L2MPPA5 L2MPPA3L2MPPA4 L2MPPA6 HEX Address Range Acronym Register Name Comments 11. Device Configuration Registers Chip-Level Registers10. CPU Megamodule Bandwidth Management Registers Recommended Operating Conditions Cvdd Recommended Operating Conditions MIN NOM MAX Unit II DC Parameter Test Conditions MIN TYP MAX UnitOH = MAX TDO DVDD33 = MIN IOL = MAX TDO Parameter Information 1 3.3-V Signal Transition Levels2 3.3-V Signal Transition Rates Tester Pin Electronics Timing Parameters and Board Routing Analysis Power-Supply Sequencing Recommended Clock and Control Signal Transition BehaviorPower Supplies Power-Supply Decoupling Product Preview Enhanced Direct Memory Access EDMA3 Controller EDMA3 Device-Specific Information Edma Binary Event Name Event Description Channel EDMA3 Channel Synchronization EventsC6454 EDMA3 Channel Synchronization Events1 EDMA3 Channel Controller Registers EDMA3 Peripheral Register DescriptionsC6454 EDMA3 Channel Synchronization Events DCHMAP34 DCHMAP32DCHMAP33 DCHMAP35 Emcr EMREmrh Emcrh Q1E0 Event Queue 1 Entry Register QSTAT2 QSTAT0QSTAT1 QSTAT3 EDMA3 Parameter RAM1 EDMA3 Parameter RAM EDMA3 Transfer Controller 0 Registers EDMA3 Transfer Controller 1 Registers EDMA3 Transfer Controller 2 Registers 109 EDMA3 Transfer Controller 3 Registers 111 10. C6454 DSP Interrupts InterruptsInterrupt Sources and Interrupt Controller Event Number Interrupt Event Interrupt Source TINTLO1 TINTLO0TINTHI0 TINTHI1 Idmabuserr L2DMPAIdmacmpa NMI External Interrupts Electrical Data/Timing11. Timing Requirements for External Interrupts1 see Figure 12. Reset Types Reset ControllerPower-on Reset POR Pin Type Initiator Warm Reset Reset Pin System Reset CPU Reset Reset Type Status Register Description Reset PriorityReset Controller Register 720 1000 Reset Electrical Data/Timing14. Timing Requirements for Reset1 2 3see -8and Figure Parameter Power-Up Timing TMS320C6454 Resetstat CLKIN1 CLKIN2 POR PLL1 and PLL1 Controller 1 PLL1 Controller Device-Specific Information Internal Clocks and Maximum Operating Frequencies 16. PLL1 Clock Frequency Ranges 1.3 PLL1 Stabilization, Lock, and Reset TimesClock Signal MIN MAX Unit 1.2 PLL1 Controller Operating Modes 2 PLL1 Controller Memory Map 17. PLL1 Stabilization, Lock, and Reset Times18. PLL1 Controller Registers Including Reset Controller MIN TYP Pllrst 3 PLL1 Controller Register Descriptions3.1 PLL1 Control Register Pllpwrdn PLL Multiplier Control Register 20. PLL Multiplier Control Register Pllm Field Descriptions Ratio PLL Pre-Divider Control RegisterPreden PLL Controller Divider 4 Register D4EN PLL Controller Divider 5 Register D5EN PLL Controller Command Register Goset PLL Controller Status Register Gostat PLL Controller Clock Align Control Register SYS5 Plldiv Ratio Change Status RegisterSYS5 SYS4 Sysclk Status Register SYS5ON SYS4ON SYS3ON SYS2ON PLL Modes Unit 29. Timing Requirements for CLKIN1 Devices1 2 3 see Figure720 850 1000 X1 Bypass X20, x25, x30 PLL2 and PLL2 Controller 1.2 PLL2 Controller Operating Modes 1 PLL2 Controller Device-Specific Information31. PLL2 Clock Frequency Ranges Pllref Pllen = 32. PLL2 Controller Registers 2 PLL2 Controller Memory Map3 PLL2 Controller Register Descriptions HEX Address Range Acronym Description PLL Controller Divider 1 Register D1EN PLL Controller Command Register ALN1 SYS1 SYS1ON 4 PLL2 Controller Input Clock Electrical Data/Timing 39. Timing Requirements for CLKIN21 2 3 see Figure DDR2 Memory Controller 1 DDR2 Memory Controller Device-Specific Information 40. DDR2 Memory Controller Registers 2 DDR2 Memory Controller Peripheral Register Descriptions3 DDR2 Memory Controller Electrical Data/Timing External Memory Interface a Emifa Emifa Device-Specific Information Emifa Peripheral Register Descriptions 41. Emifa Registers Aeclkin Emifa Electrical Data/Timing42. Timing Requirements for Aeclkin for EMIFA1 2 see Figure 720 850 1000UNIT 720Aeclkin AECLKOUT1 ABA10 AED630 Read Data Setup = Hold =ACEx ABE70 AAOE/ASOE a AAWE/ASWE a AR/W Aardy B Deasserted Aeclkout Aardya Asserted Deasserted Strobe Setup = Extended StrobeABA10 AED630 155 EA1 EA2 EA3 EA4 BE1 BE2 BE3 BE4AEA190/ABA10 ASADS/ASREB AAOE/ASOEB AAWE/ASWEB Write Latency = DSP Owns Bus HOLD/HOLDA TimingHHOLDAL-HOLDL Hold time, Hold low after Holda low Hold Holda Delay time, Aeclkout high to Abusreq valid AECLKOUTx Busreq Timing 11 I2C Peripheral 11.1 I2C Device-Specific Information I2CCLKH I2CSAR I2COARSCL I2CXSR 11.2 I2C Peripheral Register Descriptions 51. I2C Registers Standard Mode Fast Mode MIN MAX 11.3 I2C Electrical Data/Timing Unit MAX SDA SCLStop Start Repeated Stop Start Start Stop HPI Peripheral Register Descriptions Host-Port Interface HPI PeripheralHPI Device-Specific Information 54. HPI Control Registers HPI Electrical Data/Timing See -56through Figure HR/W Hhwil Hstrobea HCS HasHCNTL10 HD150 HR/W Hhwil Hstrobe a Hrdyb 46. HPI16 Write Timing has Not Used, Tied High 47. HPI16 Write Timing has Used Has input HCNTL10 input HR/W input HCS input HD310 output Hrdyb output 49. HPI32 Read Timing has Used 50. HPI32 Write Timing has Not Used, Tied High Input HCS input 51. HPI32 Write Timing has Used Input HCS input HD310 input Multichannel Buffered Serial Port McBSP McBSP Device-Specific Information 58. McBSP 1 Registers McBSP Electrical Data/Timing Product 181 Clks Clks ClkrClkx Clkx FSX Master Slave MIN MAXSlave MIN MAX Master Slave MIN Setup time, DR valid before Clkx high 18P Hold time, DR valid after Clkx high + 36P 186 Ethernet MAC Emac Ethernet Bus Emac Device-Specific Information Interface Modes Rmii 70. EMAC/MDIO Multiplexed Pins MII, RMII, and Gmii ModesBall Number Device PIN Name Interface Mode Clocking Emac Peripheral Register Descriptions 71. Ethernet MAC Emac Control Registers RX5FREEBUFFER MacconfigSoftreset RX6FREEBUFFER 72. Emac Statistics Registers HEX Address Range Acronym 02C8 2000 02C8 3FFF Emac Descriptor Memory 73. Emac Control Module Registers74. Emac Descriptor Memory Emac Electrical Data/Timing Mtclk Mrclk Input MRXD7−MRXD4GMII only Output 720 1000UNIT 1000 Mbps1000 Mbps 100/10 Mbps MRXD3−MRXD0 MTXD7−MTXD0 MTXD3−MTXD0NO.PARAMETER Emac Rmii Electrical Data/Timing Rmrefclk Mrxer Inputs 720 1000 Rmrefclk InputMRXD1-MRXD0 Mcrsdv Emac Rgmii Electrical Data/Timing Output 201 70. Emac Transmit Interface Timing Rgmii OperationAB Mdio Peripheral Register Descriptions 89. Mdio Registers Management Data Input/Output MdioMdio Device-Specific Information Mdio output Delay time, Mdclk low to Mdio data output valid 100Mdio input Timers Peripheral Register Descriptions TimersTimers Device-Specific Information 92. Timer 0 Registers TINPLx TOUTLx Timers Electrical Data/Timing94. Timing Requirements for Timer Inputs1 see Figure Peripheral Component Interconnect PCI 96. Default Values for PCI Configuration RegistersRegister Default Value PCI Device-Specific Information 97. PCI Configuration Registers PCI Peripheral Register Descriptions 98. PCI Back End Configuration Registers 99. DSP-toPCI Address Translation Registers HEX Address Offset Acronym Register Name 100. PCI Hook Configuration Registers101. PCI External Memory Space 49FF Ffff 47FF Ffff48FF Ffff 4A7F Ffff PCI Electrical Data/Timing Gpio Peripheral Register Descriptions General-Purpose Input/Output GpioGpio Device-Specific Information 102. Gpio Registers GPIx GPOx Gpio Electrical Data/Timing103. Timing Requirements for Gpio Inputs1 2 see Figure Ieee 1149.1 Jtag Compatibility Statement Ieee 1149.1 JtagJtag Device-Specific Information 105. Timing Requirements for Jtag Test Port see Figure Packaging Information Thermal Resistance Characteristics S-PBGA Package ZTZ/GTZThermal Data AIR Flow See ADDITIONS/MODIFICATIONS/DELETIONS Revision HistoryC6454 Revision History Changed -4title to EDMA3 Channel Controller Registers Product Preview Revision History 221 MSL Peak Temp Orderable Device Status PackageEco Plan QtyPage Page Important Notice