Texas Instruments TMS320C6454 warranty Product Preview

PRODUCT PREVIEW

TMS320C6454

Fixed-Point Digital Signal Processor

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SPRS311A –APRIL 2006 –REVISED DECEMBER 2006

C6454 Revision History (continued)

SEE ADDITIONS/MODIFICATIONS/DELETIONS

Section 7.7.3 PLL1 Controller Register Descriptions:

Added Values and Descriptions for RATIO bit field in Table 7-21, PLL Pre-Divider Control Register (PREDIV) Field Descriptions

Deleted PLL Controller Divider Registers section

Added new sections for PLL Controller Divider 4 Register and PLL Controller Divider 5 Register Change RATIO bit field reset to R/W-3in Figure 7-14, PLL Controller Divider 4 Register (PLLDIV4) Changed RATIO bit field reset to R/W-3in Figure 7-15, PLL Controller Divider 5 Register (PLLDIV5)

Section 7.7.4 PLL1 Controller Input and Output Clock Electrical Data/Timing:

Updated Figure 7-22, SYSCLK4 Timing

Section 7.8 PLL2 and PLL2 Controller:

Updated Notes A and B on Figure 7-23, PLL2 Block Diagram

Section 7.8.1 PLL2 Controller Device-Specific Information:

Updated Footnote (1) in Table 7-31, PLL2 Clock Frequency Ranges

Section 7.8.1.1 Internal Clocks and Maximum Operating Frequencies:

Updated paragraphs

Section 7.8.4 PLL2 Controller Input Clock Electrical Data/Timing:

Updated Footnote (3) in Table 7-39, Timing Requirements for CLKIN2

Section 7.9 DDR2 Memory Controller:

Updated paragraphs

Section 7.10.2 EMIFA Peripheral Register Description(s):

Changed Burst Priority Register acronym to BURST_PRIO in Table 7-41, EMIFA Registers

Section 7.10.3 EMIFA Electrical Data/Timing:

Updated footnotes for Table 7-45,Table 7-47and Figure 7-33,Figure 7-36,Figure 7-37, and Figure 7-38Updated Figure 7-34, Asynchronous Memory Write Timing for EMIFA

Section 7.12.2 HPI Peripheral Register Description(s):

Updated Comments for HPIC in Table 7-54, HPI Control Registers

Updated Hex Address and Comments for HPIA registers

Added Footnote (1)

Updated Footnote (2)

Section 7.12.3 HPI Electrical Data/Timing:

Changed Parameter NO. 18 MIN value to 1 ns and Parameter NO. 38 MIN value to 1.1 ns in Table 7-55, Timing Requirements for Host-Port Interface Cycles

Replaced TBD document reference with TMS320C645x DSP Host Port Interface User'sGuide (literature number SPRU969) in Figure 7-44through Figure 7-51

Section 7.13.1 McBSP Device-Specific Information:

Added paragraph

Section 7.13.2 McBSP Electrical Data/Timing:

Changed Parameter NO. 4 MAX value to 3.3 ns in Table 7-60, Switching Characteristics Over Recommended Operating Conditions for McBSP

Section 7.14.1 EMAC Device-Specific Information:

Deleted Step 1 and changed setting to clearing under Using the RMII Mode of the EMAC

Moved Table 7-70, EMAC/MDIO Multiplexed Pins (MII, RMII, and GMII Modes), under Interface Mode Select Added Interface Mode Clocking section and paragraphs

Section 7.14.2 EMAC Peripheral Register Description(s):

Corrected Hex Addresses for 02C8 0080 through 02C8 0090 in Table 7-71, Ethernet MAC (EMAC) Control Registers

Section 7.14.3.1 EMAC MII and GMII Electrical Data/Timing:

Updated Figure 7-59, MRCLK Timing (EMAC – Receive) [MII and GMII Operation]

Updated Figure 7-60, MTCLK Timing (EMAC – Transmit) [MII and GMII Operation]

Changed Table 7-77title to Switching Characteristics Over Recommended Operating Conditions for

GMTCLK - GMII Operation

Updated Figure 7-61, GMTCLK Timing (EMAC – Transmit) [GMII Operation]

Updated Figure 7-64, EMAC Transmit Interface Timing [GMII Operation]

Section 7.14.3.2 EMAC RMII Electrical Data/Timing:

Added the following tables and figures:

Table 7-82, Switching Characteristics Over Recommended Operating Conditions for EMAC RMII Transmit 10/100 Mbit/s

Figure 7-66, EMAC Transmit Interface Timing [RMII Operation]

Table 7-83, Timing Requirements for EMAC RMII Input Receive for 100 Mbps Figure 7-67, EMAC Receive Interface Timing [RMII Operation]

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