Texas Instruments TMS320C6454 warranty Aeclkin AECLKOUT1, 720 850 1000UNIT

PRODUCT

TMS320C6454

Fixed-Point Digital Signal Processor

www.ti.com

SPRS311A –APRIL 2006 –REVISED DECEMBER 2006

Table 7-43. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT for the

EMIFA Module(1) (2) (3) (see Figure 7-32)

			-720
NO.		PARAMETER	-850		UNIT
			-1000
			MIN	MAX
1	tc(EKO)	Cycle time, AECLKOUT	E – 0.7	E + 0.7	ns
2	tw(EKOH)	Pulse duration, AECLKOUT high	EH – 0.7	EH + 0.7	ns
3	tw(EKOL)	Pulse duration, AECLKOUT low	EL – 0.7	EL + 0.7	ns
4	tt(EKO)	Transition time, AECLKOUT		1	ns
5	td(EKIH-EKOH)	Delay time, AECLKIN high to AECLKOUT high	1	8	ns
6	td(EKIL-EKOL)	Delay time, AECLKIN low to AECLKOUT low	1	8	ns

(1)E = the EMIF input clock (AECLKIN or SYSCLK4) period in ns for EMIFA.

(2)The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.

(3)EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.

AECLKIN

5	1	2	3	3
4

AECLKOUT1

Figure 7-32. AECLKOUT Timing for the EMIFA Module

7.10.3.1Asynchronous Memory Timing

Table 7-44. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module(1) (2) (3)

(see Figure 7-33and Figure 7-34)

PREVIEW

NO.

3tsu(EDV-AOEH)

4th(AOEH-EDV)

5tsu(ARDY-EKOH)

6th(EKOH-ARDY)

7 tw(ARDY)

8td(ARDY-HOLD)

9tsu(ARDY-HOLD)

Setup time, AEDx valid before AAOE high

Hold time, AEDx valid after AAOE high

Setup time, AARDY valid before AECLKOUT low

Hold time, AARDY valid after AECLKOUT low

Pulse width, AARDY assertion and deassertion

Delay time, from AARDY sampled deasserted on AECLKOUT falling to beginning of programmed hold period

Setup time, before end of programmed strobe period by which AARDY should be asserted in order to insert extended strobe wait states.

-720

-850

-1000UNIT

MIN MAX

6.5ns

3ns

1ns

2ns

2E + 5 ns

4E ns

2Ens

(1)E = AECLKOUT period in ns for EMIFA

(2)To ensure data setup time, simply program the strobe width wide enough.

(3)AARDY is internally synchronized. To use AARDY as an asynchronous input, the pulse width of the AARDY signal should be at least 2E to ensure setup and hold time is met.

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