Texas Instruments TMS320C6454 warranty 155

TMS320C6454

Fixed-Point Digital Signal Processor

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SPRS311A –APRIL 2006 –REVISED DECEMBER 2006

7.10.3.2Programmable Synchronous Interface Timing

Table 7-46. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module

(see Figure 7-36)

			-720
NO.			-850	UNIT
			-1000
			MIN	MAX
6	tsu(EDV-EKOH)	Setup time, read AEDx valid before AECLKOUT high	2	ns
7	th(EKOH-EDV)	Hold time, read AEDx valid after AECLKOUT high	1.5	ns

Table 7-47. Switching Characteristics Over Recommended Operating Conditions for Programmable

Synchronous Interface Cycles for EMIFA Module(1) (see Figure 7-36–Figure7-38)

NO.

1td(EKOH-CEV)

2td(EKOH-BEV)

3td(EKOH-BEIV)

4td(EKOH-EAV)

5td(EKOH-EAIV)

8td(EKOH-ADSV)

9td(EKOH-OEV)

10td(EKOH-EDV)

11td(EKOH-EDIV)

12td(EKOH-WEV)

	-720
PARAMETER	-850		UNIT
	-1000
	MIN	MAX
Delay time, AECLKOUT high to ACEx valid	1.3	4.9	ns
Delay time, AECLKOUT high to ABEx valid		4.9	ns
Delay time, AECLKOUT high to ABEx invalid	1.3		ns
Delay time, AECLKOUT high to AEAx valid		4.9	ns
Delay time, AECLKOUT high to AEAx invalid	1.3		ns
Delay time, AECLKOUT high to ASADS/ASRE valid	1.3	4.9	ns
Delay time, AECLKOUT high to ASOE valid	1.3	4.9	ns
Delay time, AECLKOUT high to AEDx valid		4.9	ns
Delay time, AECLKOUT high to AEDx invalid	1.3		ns
Delay time, AECLKOUT high to ASWE valid	1.3	4.9	ns

PREVIEW

(1)The following parameters are programmable via the EMIFA CE Configuration registers (CEnCFG):

∙Read latency (R_LTNCY): 0-, 1-, 2-, or 3-cycle read latency

∙Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency

∙ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued (CE_EXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CE_EXT = 1).

∙Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles (R_ENABLE = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (R_ENABLE = 1).

PRODUCT

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