TMS320C6454

Fixed-Point Digital Signal Processor

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SPRS311A –APRIL 2006 –REVISED DECEMBER 2006

Table 7-83. Timing Requirements for EMAC RMII Input Receive for 100 Mbps(1) (see Figure 7-67)

NO.

1

tsu(MRXD-MREFCLK)

Setup time, receive selected signals valid before MREFCLK (at DSP)

high/low

2

th(MREFCLK-MRXD)

Hold time, receive selected signals valid after MREFCLK (at DSP) high/low

(1)For RMII, receive selected signals include: MRXD[1:0], MRXER, and MCRSDV.

3

1

RMREFCLK (Input)

4

2

3

5

 

 

MRXD1-MRXD0,

MCRSDV,

MRXER (Inputs)

-720 -850

-1000

 

UNIT

 

 

MIN

MAX

4.0

 

 

ns

2.0

 

 

ns

 

 

 

 

Figure 7-67. EMAC Receive Interface Timing [RMII Operation]

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Texas Instruments TMS320C6454 warranty Rmrefclk Input, MRXD1-MRXD0 Mcrsdv, Mrxer Inputs 720 1000