Texas Instruments TMS320C6454 Reset Controller, Power-on Reset POR Pin, Reset Types, EFFECTs

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TMS320C6454

Fixed-Point Digital Signal Processor

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SPRS311A –APRIL 2006 –REVISED DECEMBER 2006

7.6 Reset Controller

The reset controller detects the different type of resets supported on the C6454 device and manages the distribution of those resets throughout the device.

The C6454 device has several types of resets: power-on reset, warm reset, system reset, and CPU reset. Table 7-12explains further the types of reset, the reset initiator, and the effects of each reset on the chip. For more information on the effects of each reset on the PLL controllers and their clocks, see Section 7.6.7, Reset Electrical Data/Timing.

		Table 7-12. Reset Types
TYPE	INITIATOR	EFFECT(s)
Power-on Reset	POR pin	Resets the entire chip including the test and emulation logic.
Warm Reset	RESET pin	Resets everything except for the test and emulation logic and PLL2.
		Emulator stays alive during Warm Reset.
		A system reset maintains memory contents and does not reset the
System Reset	Emulator	test and emulation circuitry. The device configuration pins are also
		not re-latched and the state of the peripherals is also not affected.(1)
CPU Local Reset	HPI/PCI	CPU local reset.

(1)On the C6454 device, peripherals can be in one of several states. These states are listed in Table 3-4.

7.6.1Power-on Reset (POR Pin)

Power-on Reset is initiated by the POR pin and is used to reset the entire chip, including the test and emulation logic. Power-on Reset is also referred to as a cold reset since the device usually goes through a power-up cycle. During power-up, the POR pin must be asserted (driven low) until the power supplies have reached their normal operating conditions. Note that a device power-up cycle is not required to initiate a Power-on Reset.

The following sequence must be followed during a Power-on Reset:

1.Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted (driven low).

While POR is asserted, all pins will be set to high-impedance. After the POR pin is deasserted (driven high), all Z group pins, low group pins, and high group pins are set to their reset state and will remain at their reset state until the otherwise configured by their respective peripheral. All peripherals, except those selected for boot purposes, are disabled after a Power-on Reset and must be enabled through the Device State Control registers; for more details, see Section 3.3, Peripheral Selection After Device Reset.

2.Once all the power supplies are within valid operating conditions, the POR pin must remain asserted (low) for a minimum of 256 CLKIN2 cycles. The PLL1 controller input clock, CLKIN1, and the PCI input clock, PCLK, must also be valid during this time. PCLK is only needed if the PCI module is being used. If the DDR2 memory controller and the EMAC peripheral are not needed, CLKIN2 can be tied low and, in this case, the POR pin must remain asserted (low) for a minimum of 256 CLKIN1 cycles after all power supplies have reached valid operating conditions.

Within the low period of the POR pin, the following happens:

–The reset signals flow to the entire chip (including the test and emulation logic), resetting modules that use reset asynchronously.

–The PLL1 controller clocks are started at the frequency of the system reference clock. The clocks are propagated throughout the chip to reset modules that use reset synchronously. By default, PLL1 is in reset and unlocked.

–The PLL2 controller clocks are started at the frequency of the system reference clock. PLL2 is held in reset. Since the PLL2 controller always operates in PLL mode, the system reference clock and

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