Texas Instruments warranty TMS320C6454 L2 Memory Configurations

TMS320C6454

Fixed-Point Digital Signal Processor

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SPRS311A –APRIL 2006 –REVISED DECEMBER 2006

The L2 memory configuration for the C6454 device is as follows:

∙Port 0 configuration:

–Memory size is 1048KB

–Starting address is 0080 0000h

–2-cycle latency

–4 × 128-bit bank configuration

∙Port 1 configuration:

–Memory size is 32K bytes (this corresponds to the internal ROM)

–Starting address is 0010 0000h

–1-cycle latency

–1 × 256-bit bank configuration

L2 memory can be configured as all SRAM or as part 4-way set-associative cache. The amount of L2 memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration Register (L2CFG) of the C64x+ Megamodule. Figure 5-4shows the available SRAM/cache configurations for L2. By default, L2 is configured as all SRAM after device reset.

000

All

SRAM

L2 mode bits

001 010

31/32	15/16
	SRAM
SRAM

	4-way
4-way	cache

011

7/8

SRAM

4-way cache

111

3/4

SRAM

4-way cache

L2 memory

792K bytes

128K bytes

64K bytes

32K bytes

32K bytes

Block base address

0080 0000h

008C 0000h

008E 0000h

008F 0000h

008F 8000h

0090 0000h

PRODUCT PREVIEW

Figure 5-4. TMS320C6454 L2 Memory Configurations

For more information on the operation L1 and L2 caches, see the TMS320C64x+ DSP Cache User's Guide (literature number SPRU862).

All memory on the C6454 has a unique location in the memory map (see Table 2-2, C6454 Memory Map Summary).

When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz. Therefore, when using a software boot mode, care must be taken such that the CPU frequency does not exceed 750 MHz at any point during the boot sequence. After the boot sequence has completed, the CPU frequency can be programmed to the frequency required by the application. For more detailed information ont he boot modes, see Section 2.4, Boot Sequence.

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