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Texas Instruments TMS320C6454 warranty RSV12, RSV13, RSV14, RSV15, RSV16

Models: TMS320C6454

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PRODUCT PREVIEW

TMS320C6454

Fixed-Point Digital Signal Processor

www.ti.com

SPRS311A –APRIL 2006 –REVISED DECEMBER 2006

Table 2-3. Terminal Functions (continued)

	SIGNAL	TYPE (1) IPD/IPU (2)	DESCRIPTION
	NAME	TYPE (1) IPD/IPU (2)	DESCRIPTION
	NAME	NO.
			Reserved. This pin must be connected to the 1.8-V I/O supply (DVDD18) via a
			200-Ωresistor for proper device operation.
			NOTE: If the DDR2 Memory Controller is not used, the VREFSSTL, RSV11, and
	RSV12	C24	RSV12 pins can be connected directly to ground (VSS) to save power.
			However, connecting these pins directly to ground will prevent boundary-scan
			from functioning on the DDR2 Memory Controller pins. To preserve
			boundary-scan functionality on the DDR2 Memory Controller pins, see
			Section 7.3.4.
			Reserved. This pin must be connected to ground (VSS) via a 200-Ωresistor for
			proper device operation.
			NOTE: If the RGMII mode of the EMAC is not used, the DVDD15, VREFHSTL,
	RSV13	F2	RSV13, and RSV14 pins can be connected to directly ground (VSS) to save
			power. However, connecting these pins directly to ground will prevent
			boundary-scan from functioning on the RGMII pins of the EMAC. To preserve
			boundary-scan functionality on the RGMII pins, see Section 7.3.4.
			Reserved. This pin must be connected to the 1.5/1.8-V I/O supply (DVDD15) via
			a 200-Ωresistor for proper device operation.
			NOTE: If the RGMII mode of the EMAC is not used, the DVDD15, VREFHSTL,
	RSV14	F1	RSV13, and RSV14 pins can be connected to directly ground (VSS) to save
			power. However, connecting these pins directly to ground will prevent
			boundary-scan from functioning on the RGMII pins of the EMAC. To preserve
			boundary-scan functionality on the RGMII pins, see Section 7.3.4.
			Reserved. This pin must be connected via a 39-Ωresistor directly to ground
	RSV15	T1	(VSS) for proper device operation. The resistor used should have a minimal
			rating of 1/10 W.
			Reserved. This pin must be connected via a 20-Ωresistor directly to 3.3-V I/O
	RSV16	T2	Supply (DVDD33) for proper device operation. The resistor used should have a
			minimal rating of 1/10 W.

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Texas Instruments TMS320C6454 warranty RSV12, RSV13, RSV14, RSV15, RSV16

Contents

TMS320C6454 Fixed-Point Digital Signal Processor Features1 ZTZ/GTZ BGA Package Bottom View DescriptionZTZ/GTZ 697-PIN Ball Grid Array BGA Package Bottom View Submit Documentation Feedback Functional Block Diagram Functional Block DiagramContents Temperature Unless Otherwise NotedDevice Characteristics Characteristics of the C6454 ProcessorHardware Features C6454Fixed-Point Digital Signal Processor CPU DSP Core DescriptionProduct Preview Preview Memory Map Summary C6454 Memory Map SummaryMemory Block Description Block Size Bytes HEX Address Range 2FFF Ffff Ffff3CFF Ffff 4FFF FfffBoot Sequence Boot Modes Supported2 2nd-Level Bootloaders Pin Assignments Pin MapC6454 Pin Map Bottom View Quadrant B C6454 Pin Map Bottom View Quadrant C C6454 Pin Map Bottom View Quadrant D Signal Groups Description TMS320C6454 Fixed-Point Digital Signal Processor TINPL1 TOUTL1Gpio TOUTL0 TINPL0 SYSCLK4/GP1AACE5A ACE4A ACE3AACE2A ABE7 ABE6 ABE5 ABE4HCNTL0/PSTOP HCNTL1/PDEVSEL HHWIL/PCLK HPI16 only HpiaCLKR1/GP0 Clks SharedMdio RgmdioRgmdclk MdclkHHWIL/PCLK PidselPCBE3 HR/W/PCBE2 PINTA/GP14 HDS2/PCBE1Terminal Functions Terminal FunctionsType 1 IPD/IPU NameEmifa 64-BIT Control Signals Common to ALL Types of Memory IPD/IPU Emifa 64-BIT BUS ArbitrationEmifa 64-BIT ASYNCHRONOUS/SYNCHRONOUS Memory Control Name Emifa 64-BIT Address AEA1916AEA15 AEA14Signal Name Type 1 IPD/IPU 2DESCRIPTIONAEA6 AEA3Name Emifa 64-BIT Data IPD/IPU Description Name DDR2 Memory Controller 32-BIT Address Timer IPD/IPU Description Name DDR2 Memory Controller 32-BIT DataINTER-INTEGRATED Circuit I2C Multichannel Buffered Serial Port 1 McBSP1 Multichannel Buffered Serial Port 0 McBSP0Management Data INPUT/OUTPUT Mdio for MII/RMII/GMII Management Data INPUT/OUTPUT Mdio for RgmiiEthernet MAC Emac Rgmii Reserved for TestRSV12 RSV13RSV14 RSV15RSV17 RSV18RSV19 RSV20Supply Voltage Monitor Pins Supply Voltage PinsIPD/IPU Description E18 AA1 AA6 AB7AC6 AC9 AD5 AD7 AE6 AE8AF1 CV DDGround Pins GNDF20 F22 F24 G11 G13 G15 G17 G19 G21 G23 M16 M18 M24 M26 M29 N13 N15 N17 N19 N23 P12 P14 P16 P18 AA2 AA7 AB6AC7 AC8 AD6 AE4 AE7AF2 AH1Development Development SupportDevice Support Device and Development-Support Tool NomenclatureTemperature Range PrefixDevice Family DeviceProduct Preview Device Configuration at Device Reset C6454 Device Configuration Pins AEA190, ABA10, and PcienConfiguration IPD PIN AEA15AEA14 AEA13AEA8 AEA6Peripheral Configuration at Device Reset PCIAEA6 PIN AEA8 PIN AEA14 PIN Lower UpperPeripheral Selection After Device Reset MACSEL10 Peripheral Selection EmacPeripheral States Static Powerdown Reset Enable Progress Disabled Enabled Unlock the PERCFG0 register by Using the Perlock registerDevice State Control Registers Device State Control RegistersHEX Address Range Acronym Register Name Peripheral Lock Register Description LockvalBit Field Value Description 310 LockvalPeripheral Configuration Register 0 Description Bit FieldDescription Mode control for I2C Peripheral Configuration Register 1 Description DDR2CTL EmifactlDDR2CTL I2CSTAT Gpiostat TIMER1STAT TIMER0STAT Emacstat Peripheral Status Registers DescriptionHpistat I2CSTAT1715 Pcistat Emac Configuration Register Emaccfg Description RmiirstEmulator Buffer Powerdown Register Emubufpd Description EmuctlDevice Status Register Description Emifaen DDR2EN Pcien CFGGP2 CFGGP1 CFGGP0Sysclkout MCBSP1EN PCI66 Pcieeai MACSEL1 MACSEL0Bit Field Value Description PcieeaiMACSEL10 LendianBOOTMODE30 Jtag ID Jtagid Register DescriptionPullup/Pulldown Resistors Variant Part Number Manufacturer LSBProduct Preview Configuration Examples Timers + Emac Gmii + Mdio Internal Buses, Bridges, and Switch Fabrics System InterconnectData Switch Fabric Connections Switched Central Resource Block Diagram TMS320C6454Configuration Switch Fabric SCR Connection MatrixC64x+ Megamodule SCR Connection Priority Allocation Host EmacMemory Architecture AETSram ROM aTMS320C6454 L1P Memory Configurations TMS320C6454 L2 Memory Configurations Memory Protection Bandwidth ManagementAvailable Memory Page Protection Schemes AID0 BitPower-Down Control Megamodule ResetsMegamodule Reset Global or Local Reset Type MegamoduleMegamodule Revision Version Revision aVersion RevisionC64x+ Megamodule Register Descriptions Megamodule Interrupt RegistersMegamodule Powerdown Control Registers Megamodule Revision RegisterMegamodule Idma Registers Megamodule Cache Configuration Registers MAR168 Controls Emifa CE2 Range A800 0000 A8FF Ffff Megamodule L1/L2 Memory Protection Registers L2MPPA3 L2MPPA4L2MPPA5 L2MPPA611. Device Configuration Registers Chip-Level Registers 10. CPU Megamodule Bandwidth Management RegistersHEX Address Range Acronym Register Name Comments Recommended Operating Conditions CvddRecommended Operating Conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP MAX Unit OH = MAXII DC TDO DVDD33 = MIN IOL = MAXTDO 1 3.3-V Signal Transition Levels 2 3.3-V Signal Transition RatesParameter Information Tester Pin ElectronicsTiming Parameters and Board Routing Analysis Recommended Clock and Control Signal Transition Behavior Power SuppliesPower-Supply Sequencing Power-Supply DecouplingProduct Preview Enhanced Direct Memory Access EDMA3 Controller EDMA3 Device-Specific InformationEDMA3 Channel Synchronization Events C6454 EDMA3 Channel Synchronization Events1Edma Binary Event Name Event Description Channel EDMA3 Peripheral Register Descriptions C6454 EDMA3 Channel Synchronization EventsEDMA3 Channel Controller Registers DCHMAP32 DCHMAP33DCHMAP34 DCHMAP35EMR EmrhEmcr EmcrhQ1E0 Event Queue 1 Entry Register QSTAT0 QSTAT1QSTAT2 QSTAT3EDMA3 Parameter RAM1 EDMA3 Parameter RAM EDMA3 Transfer Controller 0 RegistersEDMA3 Transfer Controller 1 Registers EDMA3 Transfer Controller 2 Registers 109 EDMA3 Transfer Controller 3 Registers 111 Interrupts Interrupt Sources and Interrupt Controller10. C6454 DSP Interrupts Event Number Interrupt Event Interrupt SourceTINTLO0 TINTHI0TINTLO1 TINTHI1L2DMPA IdmacmpaIdmabuserr External Interrupts Electrical Data/Timing 11. Timing Requirements for External Interrupts1 see FigureNMI Reset Controller Power-on Reset POR Pin12. Reset Types Type InitiatorWarm Reset Reset Pin System Reset CPU ResetReset Priority Reset Controller RegisterReset Type Status Register Description Reset Electrical Data/Timing 14. Timing Requirements for Reset1 2 3see -8and Figure720 1000 ParameterPower-Up Timing TMS320C6454Resetstat CLKIN1 CLKIN2 PORPLL1 and PLL1 Controller 1 PLL1 Controller Device-Specific Information Internal Clocks and Maximum Operating Frequencies1.3 PLL1 Stabilization, Lock, and Reset Times Clock Signal MIN MAX Unit16. PLL1 Clock Frequency Ranges 1.2 PLL1 Controller Operating Modes17. PLL1 Stabilization, Lock, and Reset Times 18. PLL1 Controller Registers Including Reset Controller2 PLL1 Controller Memory Map MIN TYP3 PLL1 Controller Register Descriptions 3.1 PLL1 Control RegisterPllrst PllpwrdnPLL Multiplier Control Register 20. PLL Multiplier Control Register Pllm Field DescriptionsPLL Pre-Divider Control Register PredenRatio PLL Controller Divider 4 Register D4ENPLL Controller Divider 5 Register D5ENPLL Controller Command Register GosetPLL Controller Status Register GostatPLL Controller Clock Align Control Register Plldiv Ratio Change Status Register SYS5 SYS4SYS5 Sysclk Status Register SYS5ON SYS4ON SYS3ON SYS2ON29. Timing Requirements for CLKIN1 Devices1 2 3 see Figure 720 850 1000PLL Modes Unit X1 Bypass X20, x25, x30PLL2 and PLL2 Controller 1 PLL2 Controller Device-Specific Information 31. PLL2 Clock Frequency Ranges1.2 PLL2 Controller Operating Modes Pllref Pllen =2 PLL2 Controller Memory Map 3 PLL2 Controller Register Descriptions32. PLL2 Controller Registers HEX Address Range Acronym DescriptionPLL Controller Divider 1 Register D1ENPLL Controller Command Register ALN1 SYS1 SYS1ON 4 PLL2 Controller Input Clock Electrical Data/Timing 39. Timing Requirements for CLKIN21 2 3 see FigureDDR2 Memory Controller 1 DDR2 Memory Controller Device-Specific Information2 DDR2 Memory Controller Peripheral Register Descriptions 3 DDR2 Memory Controller Electrical Data/Timing40. DDR2 Memory Controller Registers External Memory Interface a Emifa Emifa Device-Specific InformationEmifa Peripheral Register Descriptions 41. Emifa RegistersEmifa Electrical Data/Timing 42. Timing Requirements for Aeclkin for EMIFA1 2 see FigureAeclkin 720 Aeclkin AECLKOUT1720 850 1000UNIT Setup = Hold = ACEx ABE70ABA10 AED630 Read Data AAOE/ASOE a AAWE/ASWE a AR/W Aardy B DeassertedStrobe Setup = Extended Strobe ABA10 AED630Aeclkout Aardya Asserted Deasserted 155 BE1 BE2 BE3 BE4 AEA190/ABA10EA1 EA2 EA3 EA4 ASADS/ASREB AAOE/ASOEB AAWE/ASWEBWrite Latency = HOLD/HOLDA Timing HHOLDAL-HOLDL Hold time, Hold low after Holda lowDSP Owns Bus Hold HoldaDelay time, Aeclkout high to Abusreq valid AECLKOUTx Busreq Timing11 I2C Peripheral 11.1 I2C Device-Specific InformationI2COAR SCLI2CCLKH I2CSAR I2CXSR11.2 I2C Peripheral Register Descriptions 51. I2C RegistersStandard Mode Fast Mode MIN MAX 11.3 I2C Electrical Data/TimingSDA SCL Stop Start RepeatedUnit MAX Stop Start Start StopHost-Port Interface HPI Peripheral HPI Device-Specific InformationHPI Peripheral Register Descriptions 54. HPI Control RegistersHPI Electrical Data/Timing See -56through Figure HCS Has HCNTL10HR/W Hhwil Hstrobea HD150HR/W Hhwil Hstrobe a Hrdyb46. HPI16 Write Timing has Not Used, Tied High 47. HPI16 Write Timing has Used Has input HCNTL10 input HR/W input HCS input HD310 output Hrdyb output49. HPI32 Read Timing has Used 50. HPI32 Write Timing has Not Used, Tied High Input HCS input51. HPI32 Write Timing has Used Input HCS input HD310 inputMultichannel Buffered Serial Port McBSP McBSP Device-Specific Information 58. McBSP 1 Registers McBSP Electrical Data/Timing Product181 Clks Clkr ClkxClks Master Slave MIN MAX Slave MIN MAXClkx FSX Master Slave MIN Setup time, DR valid before Clkx high 18P Hold time, DR valid after Clkx high + 36P186 Ethernet MAC Emac Ethernet BusEmac Device-Specific Information Interface Modes70. EMAC/MDIO Multiplexed Pins MII, RMII, and Gmii Modes Ball Number Device PIN NameRmii Interface Mode Clocking Emac Peripheral Register Descriptions 71. Ethernet MAC Emac Control RegistersMacconfig SoftresetRX5FREEBUFFER RX6FREEBUFFER72. Emac Statistics Registers HEX Address Range Acronym73. Emac Control Module Registers 74. Emac Descriptor Memory02C8 2000 02C8 3FFF Emac Descriptor Memory Emac Electrical Data/Timing MtclkOutput 720 1000UNIT 1000 Mbps 1000 Mbps 100/10 MbpsMrclk Input MRXD7−MRXD4GMII only MRXD3−MRXD0MTXD3−MTXD0 NO.PARAMETERMTXD7−MTXD0 Emac Rmii Electrical Data/Timing RmrefclkRmrefclk Input MRXD1-MRXD0 McrsdvMrxer Inputs 720 1000 Emac Rgmii Electrical Data/Timing Output201 70. Emac Transmit Interface Timing Rgmii OperationAB Management Data Input/Output Mdio Mdio Device-Specific InformationMdio Peripheral Register Descriptions 89. Mdio Registers Delay time, Mdclk low to Mdio data output valid 100 Mdio inputMdio output Timers Timers Device-Specific InformationTimers Peripheral Register Descriptions 92. Timer 0 RegistersTimers Electrical Data/Timing 94. Timing Requirements for Timer Inputs1 see FigureTINPLx TOUTLx 96. Default Values for PCI Configuration Registers Register Default ValuePeripheral Component Interconnect PCI PCI Device-Specific Information97. PCI Configuration Registers PCI Peripheral Register Descriptions98. PCI Back End Configuration Registers 99. DSP-toPCI Address Translation Registers 100. PCI Hook Configuration Registers 101. PCI External Memory SpaceHEX Address Offset Acronym Register Name 47FF Ffff 48FF Ffff49FF Ffff 4A7F FfffPCI Electrical Data/Timing General-Purpose Input/Output Gpio Gpio Device-Specific InformationGpio Peripheral Register Descriptions 102. Gpio RegistersGpio Electrical Data/Timing 103. Timing Requirements for Gpio Inputs1 2 see FigureGPIx GPOx Ieee 1149.1 Jtag Jtag Device-Specific InformationIeee 1149.1 Jtag Compatibility Statement 105. Timing Requirements for Jtag Test Port see FigureThermal Resistance Characteristics S-PBGA Package ZTZ/GTZ Thermal DataPackaging Information AIR FlowRevision History C6454 Revision HistorySee ADDITIONS/MODIFICATIONS/DELETIONS Changed -4title to EDMA3 Channel Controller Registers Product Preview Revision History 221 Orderable Device Status Package Eco PlanMSL Peak Temp QtyPage Page Important Notice