TMS320C6454

Fixed-Point Digital Signal Processor

www.ti.com

SPRS311A –APRIL 2006 –REVISED DECEMBER 2006

1.3Functional Block Diagram

Figure 1-2shows the functional block diagram of the C6454 device.

32

DDR2

 

 

 

 

 

 

 

 

 

 

 

 

C6454

DDR2 SDRAM

Mem Ctlr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PLL2 and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PLL2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Controller(D)

 

 

 

 

 

 

 

 

 

 

 

 

L2 ROM

SBSRAM

 

 

 

 

 

L1P Cache Direct-Mapped

 

 

 

 

 

 

 

 

 

 

 

32K

 

 

 

 

 

 

 

 

32K Bytes

 

 

 

 

ZBT SRAM

 

 

 

 

 

 

 

 

 

 

 

Bytes(E)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

64

EMIFA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SRAM

 

 

 

L1P Memory Controller (Memory Protect/Bandwidth Mgmt)

 

 

 

 

ROM/FLASH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O Devices

 

 

 

 

 

 

C64x+ DSP Core

 

 

 

 

 

 

 

 

 

Instruction Fetch

Control Registers

 

 

L2 Memory Controller (Memory Protect/ Bandwidth Mgmt)

 

McBSP0(A)

 

L2

 

16-/32-bit

 

SPLOOP Buffer

Exception Controller

Power Control

 

 

Instruction Dispatch

 

 

Primary Switched Central Resource

Cache

 

Instruction

 

 

 

 

 

 

 

Memory

 

 

In-Circuit Emulation

 

McBSP1(A)

M

Decode

 

 

1048K

 

 

 

 

 

 

 

e

Data Path A

Data Path B

 

 

 

Bytes

g

 

 

HPI (32/16)(B)

 

a

A Register File

B Register File

 

 

m

 

 

 

o

A31−A16

 

 

B31−B16

 

 

 

 

d

A15−A0

 

 

B15−B0

 

Interrupt and

 

Internal DMA (IDMA)

 

PCI66(B)

 

u

 

 

 

(B)

 

 

 

 

 

 

 

 

 

 

 

 

l

 

 

 

 

 

 

 

System

 

 

 

e

 

 

 

 

 

 

 

 

 

 

.L1

.S1

.M1

.D1

.D2

.M2

.S2

.L2

 

EMAC

 

xx

xx

 

 

 

 

 

 

 

 

 

 

 

 

10/100/1000

 

 

 

xx

 

 

xx

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MII

 

 

 

 

 

 

 

 

 

 

 

 

 

RMII

 

 

 

 

 

 

 

 

 

 

 

 

 

GMII

 

L1D Memory Controller (Memory Protect/Bandwidth Mgmt)

 

RMGII(D)

 

 

 

 

 

 

 

 

 

 

 

 

 

MDIO

 

 

 

 

L1D Cache

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

GPIO16(B)

 

 

 

 

2-Way

 

 

 

 

 

 

PRODUCTPREVIEW

 

 

 

 

Set-Associative

 

 

 

 

 

 

 

 

 

32K Bytes Total

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I2C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Timer1(C)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LO

 

 

EDMA 3.0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PLL1 and

 

 

Device

 

Timer0(C)

 

 

 

 

 

 

 

PLL1

 

Configuration

 

HI

 

 

Secondary

 

 

 

Controller

 

 

Logic

 

 

 

Switched Central

 

 

 

 

 

 

 

 

 

 

LO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Resource

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Boot Configuration

 

 

 

 

 

 

 

 

 

 

 

 

 

A.McBSPs: Framing Chips − H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs

B.The PCI peripheral pins are muxed with some of the HPI peripheral pins. For more detailed information, see the Device Configuration section of this document.

C.Each of the TIMER peripherals (TIMER1 and TIMER0) is configurable as either two 64-bit general-purposetimers or two 32-bit general-purpose timers or a watchdog timer.

D.The PLL2 controller also generates clocks for the EMAC.

E.When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz.

Figure 1-2. Functional Block Diagram

4

TMS320C6454 Fixed-Point Digital Signal Processor

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Texas Instruments TMS320C6454 warranty Functional Block Diagram