Texas Instruments TMS320DM355 manuals
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Texas Instruments TMS320DM355 Warranty
155 pages 1.58 Mb
1 TMS320DM355 Digital Media System-on-Chip (DMSoC)1.1 Features 1.2 Description 3 TMS320DM355Digital Media System-on-Chip (DMSoC)4 1.3 Functional Block DiagramBufferLogic TMS320DM355 Digital Media System-on-Chip (DMSoC)4Submit Documentation FeedbackSPRS463A SEPTEMBER 2007 REVISED SEPTEMBER 2007 Figure 1-1 shows the functional block diagram of the DM355 device. Figure 1-1. Functional Block Diagram 5 TMS320DM355Digital Media System-on-Chip (DMSoC)20 TMS320DM35532 TMS320DM355Table 2-17. SPI Terminal Functions (continued) The provides interface with the system clocks. Table 2-18. Clocks Terminal Functions 33 2.4.13 Real Time Output (RTO) Interface2.4.14 Pulse Width Modulator (PWM) InterfaceThe provides Real Time Output (RTO) interface. Table 2-19. RTO Terminal Functions The provides Pulse Width Modulator (PWM) interface. Table 2-20. PWM Terminal Functions 34 2.4.15 System Configuration InterfaceTable 2-20. PWM Terminal Functions (continued) 2.4.16 Emulation 35 TMS320DM355Digital Media System-on-Chip (DMSoC)Table 2-21. System/Boot Terminal Functions (continued) 36 2.5 Pin List2.6 Device Support 2.6.1 Development Tools 2.6.2 Device Nomenclature 55 TMS320DM355Digital Media System-on-Chip (DMSoC)56 2.6.3 Device Documentation59 3 Detailed Device Description91 4 Device Operating Conditions94 5 Peripheral Information and Electrical Specifications5.1 Parameter Information Device-Specific Information 5.1.1 Signal Transition Levels 96 5.2 Recommended Clock and Control Signal Transition Behavior 5.3 Power SuppliesAll clocks and control signals should transition between V and V (or between V and V 97 5.3.1 Power-Supply Sequencing98 5.4 Reset 5.4.1 Reset Electrical Data/TimingTable 5-2. Timing Requirements for Reset (see Figure 5-4 ) Figure 5-4. Reset Timing 99 5.5 Oscillators and Clocks5.5.1 MXI1 (24-MHz) Oscillator 100 5.5.2 MXI2 (27-MHz) Oscillator (optional oscillator)101 5.5.3 Clock PLL Electrical Data/Timing (Input and Output Clocks)104 5.6 General-Purpose Input/Output (GPIO)5.6.1 GPIO Peripheral Input/Output Electrical Data/Timing 105 5.6.2 GPIO Peripheral External Interrupts Electrical Data/TimingFigure 5-12. GPIO Port Timing Table 5-12. Timing Requirements for External Interrupts/EDMA Events (see Figure 5-13 ) Figure 5-13. GPIO External Interrupt Timing 106 5.7 External Memory Interface (EMIF) 5.7.1 Asynchronous EMIF (AEMIF)112 5.7.2 DDR2 Memory Controller113 5.8 MMC/SD5.8.1 MMC/SD Electrical Data/Timing 115 5.9 Video Processing Sub-System (VPSS) Overview5.9.1 Video Processing Front-End (VPFE) 120 5.9.2 Video Processing Back-End (VPBE)127 5.10 USB 2.05.10.1 USB2.0 Electrical Data/Timing 129 5.11 Universal Asynchronous Receiver/Transmitter (UART)5.11.1 UART Electrical Data/Timing 131 5.12 Serial Port Interface (SPI)5.12.1 SPI Electrical Data/Timing 134 5.13 Inter-Integrated Circuit (I2C)135 5.13.1 I2C Electrical Data/Timing5.13.1.1 Inter-Integrated Circuits (I2C) Timing Table 5-33. Timing Requirements for I2C Timings (see Figure 5-39 ) Figure 5-39. I2C Receive Timings 136 Table 5-34. Switching Characteristics for I2C Timings(see Figure 5-40 )CAUTIONThe DM355 I C pins use a standard 4-mA LVCMOS buffer, not the slow I/OP bufferdefined in the I C specification. Series resistors may be necessary to reduce noise atthe system level. Figure 5-40. I2C Transmit Timings 137 5.14 Audio Serial Port (ASP)138 5.14.1 ASP Electrical Data/Timing5.14.1.1 Audio Serial Port (ASP) Timing Table 5-35. Timing Requirements for ASP (see Figure 5-41 ) 139 Table 5-36. Switching Characteristics Over Recommended Operating Conditions for ASP(see Figure 5-41 ) Figure 5-41. ASP Timing 140 Table 5-37. ASP as SPI Timing RequirementsCLKSTP = 10b, CLKXP = 0 (see Figure 5-42 ) Table 5-38. ASP as SPI Switching CharacteristicsCLKSTP = 10b, CLKXP = 0 (see Figure 5-42 ) Figure 5-42. ASP as SPI: CLKSTP = 10b, CLKXP = 0 141 Table 5-39. ASP as SPI Timing RequirementsTable 5-40. ASP as SPI Switching CharacteristicsCLKSTP = 11b, CLKXP = 0 (see Figure 5-43 ) Figure 5-43. ASP as SPI: CLKSTP = 11b, CLKXP = 0 142 Table 5-41. ASP as SPI Timing RequirementsCLKSTP = 10b, CLKXP = 1 (see Figure 5-44 ) Table 5-42. ASP as SPI Switching CharacteristicsCLKSTP = 10b, CLKXP = 1 (see Figure 5-44 ) Figure 5-44. ASP as SPI: CLKSTP = 10b, CLKXP = 1 143 Table 5-43. ASP as SPI Timing RequirementsCLKSTP = 11b, CLKXP = 1 (see Figure 5-45 ) Table 5-44. ASP as SPI Switching CharacteristicsCLKSTP = 11b, CLKXP = 1 (see Figure 5-45 ) Figure 5-45. ASP as SPI: CLKSTP = 11b, CLKXP = 1 144 5.15 Timer5.15.1 Timer Electrical Data/Timing 145 5.16 Pulse Width Modulator (PWM)5.16.1 PWM0/1/2/3 Electrical/Timing Data 147 5.17 Real Time Out (RTO) 5.17.1 RTO Electrical/Timing DataFigure 5-49. RTO Output Timing Figure 5-50. RTO Output Delay Timing 148 5.18 IEEE 1149.1 JTAG149 5.18.1 JTAG Test-Port Electrical Data/Timing151 6 Revision History153 7 Mechanical Data7.1 Thermal Data for ZCE 7.1.1 Packaging Information
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