AMD 250 manual Tables

25112 Rev. 3.06 September 2005 Software Optimization Guide for AMD64 Processors

Tables

Table 1.	Instructions, Macro-ops and Micro-ops		5
Table 2.	Optimizations by Rank		6
Table 3.	Comparisons against Zero		55
Table 4.	Comparisons against Positive Constant		55
Table 5.	Comparisons among Two Floats		55
Table 6.	Latency of Repeated String Instructions		167
Table 7.	L1	Instruction Cache Specifications by Processor	253
Table 8.	L1	Instruction TLB Specifications	255
Table 9.	L1	Data TLB Specifications	255
Table 10.	L2	TLB Specifications by Processor	255
Table 11.	L1	Data Cache Specifications by Processor	256
Table 12.	Write-Combining Completion Events		265
Table 13.	Integer Instructions		273
Table 14.	MMX™ Technology Instructions		303
Table 15.	x87 Floating-Point Instructions		307
Table 16.	3DNow!™ Technology Instructions		314
Table 17.	3DNow!™ Technology Extensions		316
Table 18.	SSE Instructions		317
Table 19.	SSE2 Instructions		326
Table 20.	SSE3 Instructions		342
Table 21.	Clearing XMM Registers		357
Table 22.	Converting Scalar Values		364
Table 23.	Converting Vector Values		365
Table 24.	Converting Directly from Memory		365

Tables xi