AMD 250 manual 297

25112 Rev. 3.06 September 2005 Software Optimization Guide for AMD64 Processors

Table 13. Integer Instructions (Continued)

		Encoding		Decode
Syntax					Latency	Note
	First	Second	ModRM
				type
	byte	byte	byte
SETNE/SETNZ mem8	0Fh	95h	mm-xxx-xxx	DirectPath	3
SETNE/SETNZ mreg8	0Fh	95h	11-xxx-xxx	DirectPath	1
SETNO mem8	0Fh	91h	mm-xxx-xxx	DirectPath	3
SETNO mreg8	0Fh	91h	11-xxx-xxx	DirectPath	1
SETNP/SETPO mem8	0Fh	9Bh	mm-xxx-xxx	DirectPath	3
SETNP/SETPO mreg8	0Fh	9Bh	11-xxx-xxx	DirectPath	1
SETNS mem8	0Fh	99h	mm-xxx-xxx	DirectPath	3
SETNS mreg8	0Fh	99h	11-xxx-xxx	DirectPath	1
SETO mem8	0Fh	90h	mm-xxx-xxx	DirectPath	3
SETO mreg8	0Fh	90h	11-xxx-xxx	DirectPath	1
SETP/SETPE mem8	0Fh	9Ah	mm-xxx-xxx	DirectPath	3
SETP/SETPE mreg8	0Fh	9Ah	11-xxx-xxx	DirectPath	1
SETS mem8	0Fh	98h	mm-xxx-xxx	DirectPath	3
SETS mreg8	0Fh	98h	11-xxx-xxx	DirectPath	1
SGDT mem48	0Fh	01h	mm-000-xxx	VectorPath	17/18	7
SIDT mem48	0Fh	01h	mm-001-xxx	VectorPath	17/18	7
SHL/SAL mreg8, imm8	C0h		11-100-xxx	DirectPath	1	3
SHL/SAL mem8, imm8	C0h		mm-100-xxx	DirectPath	4	3
SHL/SAL mreg16/32/64, imm8	C1h		11-100-xxx	DirectPath	1	3
SHL/SAL mem16/32/64, imm8	C1h		mm-100-xxx	DirectPath	4	3
SHL/SAL mreg8, 1	D0h		11-100-xxx	DirectPath	1
SHL/SAL mem8, 1	D0h		mm-100-xxx	DirectPath	4
SHL/SAL mreg16/32/64, 1	D1h		11-100-xxx	DirectPath	1
SHL/SAL mem16/32/64, 1	D1h		mm-100-xxx	DirectPath	4

Notes:

1. Static timing assumes a predicted branch.

2. Store operation also updates ESP—the new register value is available one clock earlier than the specified latency.

3. The clock count, regardless of the number of shifts or rotates, as determined by CL or imm8.

4. LEA instructions have a latency of 1 when there are two source operands (as in the case of the base + index form LEA EAX, [EDX+EDI]). Forms with a scale or more than two source operands will have a latency of 2 (LEA EAX, [EBX+EBX*8]).

5. These instructions have an effective latency as shown. They map to internal NOPs that can be issued at a rate of three per cycle but do not occupy execution resources.

6. The latency of repeated string instructions can be found in “Latency of Repeated String Instructions” on page 167.

7. The first latency value is for 32-bit mode. The second is for 64-bit mode.

8. This opcode is used as a REX prefix in 64-bit mode.

Appendix C Instruction Latencies 297