Software Optimization Guide for AMD64 Processors

25112 Rev. 3.06 September 2005

Table 13. Integer Instructions (Continued)

 

 

Encoding

Decode

 

 

Syntax

 

 

 

Latency

Note

First

Second

ModRM

type

 

 

 

 

byte

byte

byte

 

 

 

 

 

 

 

 

 

 

IDIV mem16/32/64

F7h

 

mm-111-xxx

VectorPath

27/43/

 

 

 

 

 

 

75

 

 

 

 

 

 

 

 

IMUL reg16, imm16

69h

 

11-xxx-xxx

VectorPath

4

 

 

 

 

 

 

 

 

IMUL reg32/64, imm32/(32 sign extended)

69h

 

11-xxx-xxx

DirectPath

3/4

 

 

 

 

 

 

 

 

IMUL reg16, mreg16, imm16

69h

 

11-xxx-xxx

VectorPath

4

 

 

 

 

 

 

 

 

IMUL reg32/64, mreg32/64, imm32/(32 sign

69h

 

11-xxx-xxx

DirectPath

3/4

 

extended)

 

 

 

 

 

 

 

 

 

 

 

 

 

IMUL reg16/32/64, mem16/32/64,

69h

 

mm-xxx-xxx

VectorPath

7/7/8

 

imm16/32/(32 sign extended)

 

 

 

 

 

 

 

 

 

 

 

 

 

IMUL reg16/32/64, imm8 (sign extended)

6Bh

 

11-xxx-xxx

VectorPath

4/3/4

 

 

 

 

 

 

 

 

IMUL reg16/32/64, mreg16/32/64, imm8

6Bh

 

11-xxx-xxx

VectorPath

4/3/4

 

(signed)

 

 

 

 

 

 

 

 

 

 

 

 

 

IMUL reg16/32/64, mem16/32/64, imm8

6Bh

 

mm-xxx-xxx

VectorPath

7/7/8

 

(signed)

 

 

 

 

 

 

 

 

 

 

 

 

 

IMUL mreg8

F6h

 

11-101-xxx

DirectPath

3

 

 

 

 

 

 

 

 

IMUL mem8

F6h

 

mm-101-xxx

DirectPath

6

 

 

 

 

 

 

 

 

IMUL mreg16

F7h

 

11-101-xxx

VectorPath

4

 

 

 

 

 

 

 

 

IMUL mreg32/64

F7h

 

11-101-xxx

Double

3/5

 

 

 

 

 

 

 

 

IMUL mem16

F7h

 

mm-101-xxx

VectorPath

7

 

 

 

 

 

 

 

 

IMUL mem32/64

F7h

 

mm-101-xxx

Double

6/8

 

 

 

 

 

 

 

 

IMUL reg16/32/64, mreg16/32/64

0Fh

AFh

11-xxx-xxx

DirectPath

3/3/4

 

 

 

 

 

 

 

 

IMUL reg16/32/64, mem16/32/64

0Fh

AFh

mm-xxx-xxx

DirectPath

6/6/7

 

 

 

 

 

 

 

 

IN AL, imm8

E4h

 

 

VectorPath

184

 

 

 

 

 

 

 

 

IN AX, imm8

E5h

 

 

VectorPath

184

 

 

 

 

 

 

 

 

IN EAX, imm8

E5h

 

 

VectorPath

184

 

 

 

 

 

 

 

 

Notes:

 

 

 

 

 

 

1.Static timing assumes a predicted branch.

2.Store operation also updates ESP—the new register value is available one clock earlier than the specified latency.

3.The clock count, regardless of the number of shifts or rotates, as determined by CL or imm8.

4.LEA instructions have a latency of 1 when there are two source operands (as in the case of the base + index form LEA EAX, [EDX+EDI]). Forms with a scale or more than two source operands will have a latency of 2 (LEA EAX, [EBX+EBX*8]).

5.These instructions have an effective latency as shown. They map to internal NOPs that can be issued at a rate of three per cycle but do not occupy execution resources.

6.The latency of repeated string instructions can be found in “Latency of Repeated String Instructions” on page 167.

7.The first latency value is for 32-bit mode. The second is for 64-bit mode.

8.This opcode is used as a REX prefix in 64-bit mode.

282

Instruction Latencies

Appendix C

Page 298
Image 298
AMD 250 manual 282