288 Instruction Latencies Appendix C25112 Rev. 3.06 September 2005
Software Optimization Guide for AMD64 Processors
MOV DH, imm8 B6h DirectPath 1
MOV BH, imm8 B7h DirectPath 1
MOV AX/EAX/RAX/R8, imm16/32/64 B8h DirectPath 1
MOV CX/ECX/RCX/R9, imm16/32/64 B9h DirectPath 1
MOV DX/EDX/RDX/R10, imm16/32/64 BAh DirectPath 1
MOV BX/EBX/RBX/R11, imm16/32/64 BBh DirectPath 1
MOV SP/ESP/RSP/R12, imm16/32/64 BCh DirectPath 1
MOV BP/EBP/RBP/R13, imm16/32/64 BDh DirectPath 1
MOV SI/ESI/RSI/R14, imm16/32/64 BEh DirectPath 1
MOV DI/EDI/RDI/R15, imm16/32/64 BFh DirectPath 1
MOV mreg8, imm8 C6h 11-000-xxx DirectPath 1
MOV mem8, imm8 C6h mm-000-xxx DirectPath 3
MOV mreg16/32/64, imm16/32 C7h 11-000-xxx DirectPath 1
MOV mem16/32/64, imm16/32 C7h mm-000-xxx DirectPath 3
MOVSB/MOVS mem8, mem8 A4h VectorPath 5 6
MOVSD/MOVS mem16, mem16 A5h VectorPath 5 6
MOVSW/MOVS mem32, mem32 A5h VectorPath 5 6
MOVSQ/MOVS mem64, mem64 A5h VectorPath ~ 6
MOVSX reg16/32/64, mreg8 0Fh BEh 11-xxx-xxx DirectPath 1
MOVSX reg16/32/64, mem8 0Fh BEh mm-xxx-xxx DirectPath 4
MOVSX reg32/64, mreg16 0Fh BFh 11-xxx-xxx DirectPath 1
MOVSX reg32/64, mem16 0Fh BFh mm-xxx-xxx DirectPath 4
MOVSXD reg64, mreg32 63h DirectPath 1
MOVSXD reg64, mem32 63h DirectPath 4
Table 13. Integer Instructions (Continued)
Syntax
Encoding
Decode
type Latency Note
First
byte
Second
byte
ModRM
byte
Notes:
1. Static timing assumes a predicted branch.
2. Store operation also updates ESP—the new register value is available one clock earlier than the specified
latency.
3. The clock count, regardless of the number of shifts or rotates, as determined by CL or imm8.
4. LEA instructions have a latency of 1 when there are two source operands (as in the case of the base + index
form LEA EAX, [EDX+EDI]). Forms with a scale or more than two source operands will have a latency of 2 (LEA
EAX, [EBX+EBX*8]).
5. These instructions have an effective latency as shown. They map to internal NOPs that can be issued at a rate of
three per cycle but do not occupy execution resources.
6. The latency of repeated string instructions can be found in “Latency of Repeated String Instructions” on
page 167.
7. The first latency value is for 32-bit mode. The second is for 64-bit mode.
8. This opcode is used as a REX prefix in 64-bit mode.