AMD 250 manual 330, Fadd Fmul Fstore

Software Optimization Guide for AMD64 Processors 25112 Rev. 3.06 September 2005

Table 19. SSE2 Instructions (Continued)

		Encoding					Latency	Throughput
Syntax					Decode	FPU			Note
	Prefix	First	2nd
				ModRM byte	type	pipe(s)
	byte	byte	byte
MOVD xmmreg, reg32	66h	0Fh	6Eh	11-xxx-xxx	VectorPath	~	9
MOVD xmmreg, mem32	66h	0Fh	6Eh	mm-xxx-xxx	Double	FADD/	4
						FMUL/
						FSTORE
MOVD reg32, xmmreg	66h	0Fh	7Eh	11-xxx-xxx	Double	FSTORE	4
MOVD mem32, xmmreg	66h	0Fh	7Eh	mm-xxx-xxx	DirectPath	FSTORE	2
MOVD xmmreg, reg64	66h	0Fh	6Eh	11-xxx-xxx	VectorPath	~	9
MOVD xmmreg, mem64	66h	0Fh	6Eh	mm-xxx-xxx	Double	FADD/	4
						FMUL/
						FSTORE
MOVD reg64, xmmreg	66h	0Fh	7Eh	11-xxx-xxx	Double	FSTORE	4
MOVD mem64, xmmreg	66h	0Fh	7Eh	mm-xxx-xxx	DirectPath	FSTORE	2
MOVDQ2Q mmreg,	F2h	0Fh	D6h	11-xxx-xxx	DirectPath	FADD/	2
xmmreg						FMUL
MOVDQA xmmreg1,	66h	0Fh	6Fh	11-xxx-xxx	Double	FADD/	2
xmmreg2						FMUL
MOVDQA xmmreg,	66h	0Fh	6Fh	mm-xxx-xxx	Double	FADD/	2
mem128						FMUL/
						FSTORE
MOVDQA xmmreg1,	66h	0Fh	7Fh	11-xxx-xxx	Double	FADD/	2
xmmreg2						FMUL
MOVDQA mem128,	66h	0Fh	7Fh	mm-xxx-xxx	Double	FSTORE	3
xmmreg
MOVDQU xmmreg1,	F3h	0Fh	6Fh	11-xxx-xxx	Double	FADD/	2
xmmreg2						FMUL
MOVDQU xmmreg,	F3h	0Fh	6Fh	mm-xxx-xxx	VectorPath	~	7
mem128
MOVDQU xmmreg1,	F3h	0Fh	7Fh	11-xxx-xxx	Double	FADD/	2
xmmreg2						FMUL
MOVDQU mem128,	F3h	0Fh	7Fh	mm-xxx-xxx	VectorPath	FSTORE	4
xmmreg
MOVHPD xmmreg,	66h	0Fh	16h	mm-xxx-xxx	DirectPath	FADD/	2
mem64						FMUL/
						FSTORE

Notes:

1. The low half of the result is available one cycle earlier than listed.

2. This is the execution latency for the instruction. The time to complete the external write depends on the memory speed and the hardware implementation.

330 Instruction Latencies Appendix C