AMD 250 manual 338

Software Optimization Guide for AMD64 Processors 25112 Rev. 3.06 September 2005

Table 19. SSE2 Instructions (Continued)

		Encoding					Latency	Throughput
Syntax					Decode	FPU			Note
	Prefix	First	2nd
				ModRM byte	type	pipe(s)
	byte	byte	byte
PSRAW xmmreg,	66h	0Fh	E1h		Double	FADD/	4	1/1
mem128						FMUL
PSRAW xmmreg, imm8	66h	0Fh	71h	11-100-xxx	Double	FADD/	2	1/1
						FMUL
PSRLD xmmreg1,	66h	0Fh	D2h		Double	FADD/	2	1/1
xmmreg2						FMUL
PSRLD xmmreg,	66h	0Fh	D2h		Double	FADD/	4	1/1
mem128						FMUL
PSRLD xmmreg, imm8	66h	0Fh	72h	11-010-xxx	Double	FADD/	2	1/1
						FMUL
PSRLDQ xmmreg,	66h	0Fh	73h	11-011-xxx	Double	FADD/	2	1/1
imm8						FMUL
PSRLQ xmmreg1,	66h	0Fh	D3h		Double	FADD/	2	1/1
xmmreg2						FMUL
PSRLQ xmmreg,	66h	0Fh	D3h		Double	FADD/	4	1/1
mem128						FMUL
PSRLQ xmmreg, imm8	66h	0Fh	73h	11-010-xxx	Double	FADD/	2	1/1
						FMUL
PSRLW xmmreg1,	66h	0Fh	D1h		Double	FADD/	2	1/1
xmmreg2						FMUL
PSRLW xmmreg,	66h	0Fh	D1h		Double	FADD/	4	1/1
mem128						FMUL
PSRLW xmmreg, imm8	66h	0Fh	71h	11-010-xxx	Double	FADD/	2	1/1
						FMUL
PSUBB xmmreg1,	66h	0Fh	F8h		Double	FADD/	2	1/1
xmmreg2						FMUL
PSUBB xmmreg,	66h	0Fh	F8h		Double	FADD/	4	1/1
mem128						FMUL
PSUBD xmmreg1,	66h	0Fh	FAh		Double	FADD/	2	1/1
xmmreg2						FMUL
PSUBD xmmreg,	66h	0Fh	FAh		Double	FADD/	4	1/1
mem128						FMUL
PSUBQ mmreg1,	0Fh	FBh			DirectPath	FADD/	2	1/1
mmreg2						FMUL

Notes:

1. The low half of the result is available one cycle earlier than listed.

2. This is the execution latency for the instruction. The time to complete the external write depends on the memory speed and the hardware implementation.

338 Instruction Latencies Appendix C