AMD 250 manual 276

Software Optimization Guide for AMD64 Processors 25112 Rev. 3.06 September 2005

Table 13. Integer Instructions (Continued)

		Encoding		Decode
Syntax					Latency	Note
	First	Second	ModRM
				type
	byte	byte	byte
BSWAP EBP/RBP/R13	0Fh	CDh		DirectPath	1
BSWAP EBX/RBX/R11	0Fh	CBh		DirectPath	1
BSWAP ECX/RCX/R9	0Fh	C9h		DirectPath	1
BSWAP EDI/RDI/R15	0Fh	CFh		DirectPath	1
BSWAP EDX/RDX/R10	0Fh	CAh		DirectPath	1
BSWAP ESI/RSI/R14	0Fh	CEh		DirectPath	1
BSWAP ESP/RSP/R12	0Fh	CCh		DirectPath	1
BT mreg16/32/64, reg16/32/64	0Fh	A3h	11-xxx-xxx	DirectPath	1
BT mem16/32/64, reg16/32/64	0Fh	A3h	mm-xxx-xxx	VectorPath	8
BT mreg16/32/64, imm8	0Fh	BAh	11-100-xxx	DirectPath	1
BT mem16/32/64, imm8	0Fh	BAh	mm-100-xxx	DirectPath	4
BTC mreg16/32/64, reg16/32/64	0Fh	BBh	11-xxx-xxx	Double	2
BTC mem16/32/64, reg16/32/64	0Fh	BBh	mm-xxx-xxx	VectorPath	9
BTC mreg16/32/64, imm8	0Fh	BAh	11-111-xxx	Double	2
BTC mem16/32/64, imm8	0Fh	BAh	mm-111-xxx	VectorPath	5
BTR mreg16/32/64, reg16/32/64	0Fh	B3h	11-xxx-xxx	Double	2
BTR mem16/32/64, reg16/32/64	0Fh	B3h	mm-xxx-xxx	VectorPath	9
BTR mreg16/32/64, imm8	0Fh	BAh	11-110-xxx	Double	2
BTR mem16/32/64, imm8	0Fh	BAh	mm-110-xxx	VectorPath	5
BTS mreg16/32/64, reg16/32/64	0Fh	ABh	11-xxx-xxx	Double	2
BTS mem16/32/64, reg16/32/64	0Fh	ABh	mm-xxx-xxx	VectorPath	9
BTS mreg16/32/64, imm8	0Fh	BAh	11-101-xxx	Double	2
BTS mem16/32/64, imm8	0Fh	BAh	mm-101-xxx	VectorPath	5
CALL disp16/32 (near, displacement)	E8h			VectorPath	3	2

Notes:

1. Static timing assumes a predicted branch.

2. Store operation also updates ESP—the new register value is available one clock earlier than the specified latency.

3. The clock count, regardless of the number of shifts or rotates, as determined by CL or imm8.

4. LEA instructions have a latency of 1 when there are two source operands (as in the case of the base + index form LEA EAX, [EDX+EDI]). Forms with a scale or more than two source operands will have a latency of 2 (LEA EAX, [EBX+EBX*8]).

5. These instructions have an effective latency as shown. They map to internal NOPs that can be issued at a rate of three per cycle but do not occupy execution resources.

6. The latency of repeated string instructions can be found in “Latency of Repeated String Instructions” on page 167.

7. The first latency value is for 32-bit mode. The second is for 64-bit mode.

8. This opcode is used as a REX prefix in 64-bit mode.

276 Instruction Latencies Appendix C