AMD 250 manual 279, CMP reg16/32/64, mreg16/32/64

25112 Rev. 3.06 September 2005 Software Optimization Guide for AMD64 Processors

Table 13. Integer Instructions (Continued)

		Encoding		Decode
Syntax					Latency	Note
	First	Second	ModRM
				type
	byte	byte	byte
CMOVNS reg16/32/64, mem16/32/64	0Fh	49h	mm-xxx-xxx	DirectPath	4
CMOVNS reg16/32/64, reg16/32/64	0Fh	49h	11-xxx-xxx	DirectPath	1
CMOVO reg16/32/64, mem16/32/64	0Fh	40h	mm-xxx-xxx	DirectPath	4
CMOVO reg16/32/64, reg16/32/64	0Fh	40h	11-xxx-xxx	DirectPath	1
CMOVP/CMOVPE reg16/32/64, mem16/32/64	0Fh	4Ah	mm-xxx-xxx	DirectPath	4
CMOVP/CMOVPE reg16/32/64, reg16/32/64	0Fh	4Ah	11-xxx-xxx	DirectPath	1
CMOVS reg16/32/64, mem16/32/64	0Fh	48h	mm-xxx-xxx	DirectPath	4
CMOVS reg16/32/64, reg16/32/64	0Fh	48h	11-xxx-xxx	DirectPath	1
CMP mem8, reg8	38h		mm-xxx-xxx	DirectPath	4
CMP mreg8, reg8	38h		11-xxx-xxx	DirectPath	1
CMP mem16/32/64, reg16/32/64	39h		mm-xxx-xxx	DirectPath	4
CMP mreg16/32/64, reg16/32/64	39h		11-xxx-xxx	DirectPath	1
CMP reg8, mem8	3Ah		mm-xxx-xxx	DirectPath	4
CMP reg8, mreg8	3Ah		11-xxx-xxx	DirectPath	1
CMP reg16/32/64, mem16/32/64	3Bh		mm-xxx-xxx	DirectPath	4
CMP reg16/32/64, mreg16/32/64	3Bh		11-xxx-xxx	DirectPath	1
CMP AL, imm8	3Ch			DirectPath	1
CMP AX/EAX, imm16/32	3Dh			DirectPath	1
CMP RAX, imm32 (sign extended)	3Dh			DirectPath	1
CMP mem8, imm8	80h		mm-111-xxx	DirectPath	4
CMP mreg8, imm8	80h		11-111-xxx	DirectPath	1
CMP mem16/32/64, imm16/32	81h		mm-111-xxx	DirectPath	4
CMP mreg16/32/64, imm16/32	81h		11-111-xxx	DirectPath	1
CMP mem16/32/64, imm8 (sign extended)	83h		mm-111-xxx	DirectPath	4

Notes:

1. Static timing assumes a predicted branch.

2. Store operation also updates ESP—the new register value is available one clock earlier than the specified latency.

3. The clock count, regardless of the number of shifts or rotates, as determined by CL or imm8.

4. LEA instructions have a latency of 1 when there are two source operands (as in the case of the base + index form LEA EAX, [EDX+EDI]). Forms with a scale or more than two source operands will have a latency of 2 (LEA EAX, [EBX+EBX*8]).

5. These instructions have an effective latency as shown. They map to internal NOPs that can be issued at a rate of three per cycle but do not occupy execution resources.

6. The latency of repeated string instructions can be found in “Latency of Repeated String Instructions” on page 167.

7. The first latency value is for 32-bit mode. The second is for 64-bit mode.

8. This opcode is used as a REX prefix in 64-bit mode.

Appendix C Instruction Latencies 279