AMD 250 manual 274, ADD reg16/32/64, mem16/32/64

Software Optimization Guide for AMD64 Processors 25112 Rev. 3.06 September 2005

Table 13. Integer Instructions (Continued)

		Encoding		Decode
Syntax					Latency	Note
	First	Second	ModRM
				type
	byte	byte	byte
ADC mreg16/32/64, imm8 (sign extended)	83h		11-010-xxx	DirectPath	1
ADC mem16/32/64, imm8 (sign extended)	83h		mm-010-xxx	DirectPath	4
ADD mreg8, reg8	00h		11-xxx-xxx	DirectPath	1
ADD mem8, reg8	00h		mm-xxx-xxx	DirectPath	4
ADD mreg16/32/64, reg16/32/64	01h		11-xxx-xxx	DirectPath	1
ADD mem16/32/64, reg16/32/64	01h		mm-xxx-xxx	DirectPath	4
ADD reg8, mreg8	02h		11-xxx-xxx	DirectPath	1
ADD reg8, mem8	02h		mm-xxx-xxx	DirectPath	4
ADD reg16/32/64, mreg16/32/64	03h		11-xxx-xxx	DirectPath	1
ADD reg16/32/64, mem16/32/64	03h		mm-xxx-xxx	DirectPath	4
ADD AL, imm8	04h			DirectPath	1
ADD AX, imm16	05h			DirectPath	1
ADD EAX, imm32	05h			DirectPath	1
ADD RAX, imm32 (sign extended)	05h			DirectPath	1
ADD mreg8, imm8	80h		11-000-xxx	DirectPath	1
ADD mem8, imm8	80h		mm-000-xxx	DirectPath	4
ADD mreg16/32/64, imm16/32	81h		11-000-xxx	DirectPath	1
ADD mem16/32/64, imm16/32	81h		mm-000-xxx	DirectPath	4
ADD mreg16/32/64, imm8 (sign extended)	83h		11-000-xxx	DirectPath	1
ADD mem16/32/64, imm8 (sign extended)	83h		mm-000-xxx	DirectPath	4
AND mreg8, reg8	20h		11-xxx-xxx	DirectPath	1
AND mem8, reg8	20h		mm-xxx-xxx	DirectPath	4
AND mreg16/32/64, reg16/32/64	21h		11-xxx-xxx	DirectPath	1
AND mem16/32/64, reg16/32/64	21h		mm-xxx-xxx	DirectPath	4

Notes:

1. Static timing assumes a predicted branch.

2. Store operation also updates ESP—the new register value is available one clock earlier than the specified latency.

3. The clock count, regardless of the number of shifts or rotates, as determined by CL or imm8.

4. LEA instructions have a latency of 1 when there are two source operands (as in the case of the base + index form LEA EAX, [EDX+EDI]). Forms with a scale or more than two source operands will have a latency of 2 (LEA EAX, [EBX+EBX*8]).

5. These instructions have an effective latency as shown. They map to internal NOPs that can be issued at a rate of three per cycle but do not occupy execution resources.

6. The latency of repeated string instructions can be found in “Latency of Repeated String Instructions” on page 167.

7. The first latency value is for 32-bit mode. The second is for 64-bit mode.

8. This opcode is used as a REX prefix in 64-bit mode.

274 Instruction Latencies Appendix C