AMD 250 manual SSE2 Instructions, 326

Software Optimization Guide for AMD64 Processors 25112 Rev. 3.06 September 2005

C.8	SSE2 Instructions
Table 19.	SSE2 Instructions
			Encoding					Latency	Throughput
Syntax						Decode	FPU			Note
		Prefix	First	2nd
					ModRM byte	type	pipe(s)
		byte	byte	byte
ADDPD xmmreg1,		66h	0Fh	58h	11-xxx-xxx	Double	FADD	5	1/2
xmmreg2
ADDPD xmmreg,		66h	0Fh	58h	mm-xxx-xxx	Double	FADD	7	1/2
mem128
ADDSD xmmreg1,		F2h	0Fh	58h	11-xxx-xxx	DirectPath	FADD	4	1/1
xmmreg2
ADDSD xmmreg,		F2h	0Fh	58h	mm-xxx-xxx	DirectPath	FADD	6	1/1
mem64
ANDNPD xmmreg1,		66h	0Fh	55h	11-xxx-xxx	Double	FMUL	3	1/2
xmmreg2
ANDNPD xmmreg,		66h	0Fh	55h	mm-xxx-xxx	Double	FMUL	5	1/2
mem128
ANDPD xmmreg1,		66h	0Fh	54h	11-xxx-xxx	Double	FMUL	3	1/2
xmmreg2
ANDPD xmmreg,		66h	0Fh	54h	mm-xxx-xxx	Double	FMUL	5	1/2
mem128
CMPPD xmmreg1,		66h	0Fh	C2h	11-xxx-xxx	Double	FADD	3	1/2
xmmreg2, imm8
CMPPD xmmreg,		66h	0Fh	C2h	mm-xxx-xxx	Double	FADD	5	1/2
mem128, imm8
CMPSD xmmreg1,		F2h	0Fh	C2h	11-xxx-xxx	DirectPath	FADD	2	1/1
xmmreg2, imm8
CMPSD xmmreg,		F2h	0Fh	C2h	mm-xxx-xxx	DirectPath	FADD	4	1/1
mem64, imm8
COMISD xmmreg1,		66h	0Fh	2Fh	11-xxx-xxx	VectorPath	FADD	4	1
xmmreg2
COMISD xmmreg,		66h	0Fh	2Fh	mm-xxx-xxx	VectorPath	FADD	5	1
mem64
CVTDQ2PD xmmreg1,		F3h	0Fh	E6h	11-xxx-xxx	Double	FSTORE	5	1/2
xmmreg2
CVTDQ2PD xmmreg,		F3h	0Fh	E6h	mm-xxx-xxx	Double	FSTORE	7	1/2
mem64
Notes:
1. The low half of the result is available one cycle earlier than listed.
2. This is the execution latency for the instruction. The time to complete the external write depends on the memory
speed and the hardware implementation.

326 Instruction Latencies Appendix C