Software Optimization Guide for AMD64 Processors

25112 Rev. 3.06 September 2005

Table 13. Integer Instructions (Continued)

 

 

Encoding

Decode

 

 

Syntax

 

 

 

Latency

Note

First

Second

ModRM

type

 

 

 

 

byte

byte

byte

 

 

 

 

 

 

 

 

 

 

JA/JNBE disp8

77h

 

 

DirectPath

1

1

 

 

 

 

 

 

 

JA/JNBE disp16/32

0Fh

87h

 

DirectPath

1

1

 

 

 

 

 

 

 

JAE/JNB/JNC disp8

73h

 

 

DirectPath

1

1

 

 

 

 

 

 

 

JAE/JNB/JNC disp16/32

0Fh

83h

 

DirectPath

1

1

 

 

 

 

 

 

 

JB/JC/JNAE disp8

72h

 

 

DirectPath

1

1

 

 

 

 

 

 

 

JB/JC/JNAE disp16/32

0Fh

82h

 

DirectPath

1

1

 

 

 

 

 

 

 

JBE/JNA disp8

76h

 

 

DirectPath

1

1

 

 

 

 

 

 

 

JBE/JNA disp16/32

0Fh

86h

 

DirectPath

1

1

 

 

 

 

 

 

 

JCXZ/JECXZ/JRCXZ disp8

E3h

 

 

DirectPath

2

1

 

 

 

 

 

 

 

JE/JZ disp8

74h

 

 

DirectPath

1

1

 

 

 

 

 

 

 

JE/JZ disp16/32

0Fh

84h

 

DirectPath

1

1

 

 

 

 

 

 

 

JG/JNLE disp8

7Fh

 

 

DirectPath

1

1

 

 

 

 

 

 

 

JG/JNLE disp16/32

0Fh

8Fh

 

DirectPath

1

1

 

 

 

 

 

 

 

JGE/JNL disp8

7Dh

 

 

DirectPath

1

1

 

 

 

 

 

 

 

JGE/JNL disp16/32

0Fh

8Dh

 

DirectPath

1

1

 

 

 

 

 

 

 

JL/JNGE disp8

7Ch

 

 

DirectPath

1

1

 

 

 

 

 

 

 

JL/JNGE disp16/32

0Fh

8Ch

 

DirectPath

1

1

 

 

 

 

 

 

 

JLE/JNG disp8

7Eh

 

 

DirectPath

1

1

 

 

 

 

 

 

 

JLE/JNG disp16/32

0Fh

8Eh

 

DirectPath

1

1

 

 

 

 

 

 

 

JMP disp8 (short)

EBh

 

 

DirectPath

1

 

 

 

 

 

 

 

 

JMP disp16/32 (near, displacement)

E9h

 

 

DirectPath

1

 

 

 

 

 

 

 

 

JMP mem16/32/64 (near, indirect)

FFh

 

mm-100-xxx

DirectPath

4

 

 

 

 

 

 

 

 

JMP mreg16/32/64 (near, indirect)

FFh

 

11-100-xxx

DirectPath

1

 

 

 

 

 

 

 

 

JMP mem16:16/32 (far, indirect, no call gate)

FFh

 

mm-101-xxx

VectorPath

34

 

 

 

 

 

 

 

 

Notes:

1. Static timing assumes a predicted branch.

2. Store operation also updates ESP—the new register value is available one clock earlier than the specified latency.

3. The clock count, regardless of the number of shifts or rotates, as determined by CL or imm8.

4. LEA instructions have a latency of 1 when there are two source operands (as in the case of the base + index form LEA EAX, [EDX+EDI]). Forms with a scale or more than two source operands will have a latency of 2 (LEA EAX, [EBX+EBX*8]).

5. These instructions have an effective latency as shown. They map to internal NOPs that can be issued at a rate of three per cycle but do not occupy execution resources.

6. The latency of repeated string instructions can be found in “Latency of Repeated String Instructions” on page 167.

7. The first latency value is for 32-bit mode. The second is for 64-bit mode.

8. This opcode is used as a REX prefix in 64-bit mode.

284

Instruction Latencies

Appendix C

Page 299 Page 301
Page 300
Image 300
AMD 250 manual 284, JA/JNBE disp16/32
Page 299 Page 301
Top Page Image Contents