AMD 250 manual 286

Software Optimization Guide for AMD64 Processors 25112 Rev. 3.06 September 2005

Table 13. Integer Instructions (Continued)

		Encoding		Decode
Syntax					Latency	Note
	First	Second	ModRM
				type
	byte	byte	byte
LEAVE (32 or 64 bit stack size)	C9h			Double	3
LES reg16/32, mem32/48	C4h		mm-xxx-xxx	VectorPath	~
LFS reg16/32, mem32/48	0Fh	B4h		VectorPath	~
LGDT mem16:32	0Fh	01h	mm-010-xxx	VectorPath	37
LGDT mem16:64	0Fh	01h	mm-010-xxx	VectorPath	~
LGS reg16/32, mem32/48	0Fh	B5h		VectorPath	~
LIDT mem16:32	0Fh	01h	mm-011-xxx	VectorPath	148
LIDT mem16:64	0Fh	01h	mm-011-xxx	VectorPath	~
LLDT mreg16	0Fh	00h	11-010-xxx	VectorPath	34
LLDT mem16	0Fh	00h	mm-010-xxx	VectorPath	35
LMSW mreg16	0Fh	01h	11-100-xxx	VectorPath	11
LMSW mem16	0Fh	01h	mm-100-xxx	VectorPath	12
LODS/LODSB mem8	ACh			VectorPath	5	6
LODS/LODSW mem16	ADh			VectorPath	5	6
LODS/LODSD mem32	ADh			VectorPath	4	6
LODS/LODSQ mem64	ADh			VectorPath	~	6
LOOP disp8	E2h			VectorPath	9/8	7
LOOPE/LOOPZ disp8	E1h			VectorPath	9/8	7
LOOPNE/LOOPNZ disp8	E0h			VectorPath	9/8	7
LSL reg16/32/64, mreg16/32	0Fh	03h	11-xxx-xxx	VectorPath	21
LSL reg16/32/64, mem16/32	0Fh	03h	mm-xxx-xxx	VectorPath	23
LSS reg16/32/64, mem16:16/32	0Fh	B2h	mm-xxx-xxx	VectorPath	~
LTR mreg16	0Fh	00h	11-011-xxx	VectorPath	~
LTR mem16	0Fh	00h	mm-011-xxx	VectorPath	~

Notes:

1. Static timing assumes a predicted branch.

2. Store operation also updates ESP—the new register value is available one clock earlier than the specified latency.

3. The clock count, regardless of the number of shifts or rotates, as determined by CL or imm8.

4. LEA instructions have a latency of 1 when there are two source operands (as in the case of the base + index form LEA EAX, [EDX+EDI]). Forms with a scale or more than two source operands will have a latency of 2 (LEA EAX, [EBX+EBX*8]).

5. These instructions have an effective latency as shown. They map to internal NOPs that can be issued at a rate of three per cycle but do not occupy execution resources.

6. The latency of repeated string instructions can be found in “Latency of Repeated String Instructions” on page 167.

7. The first latency value is for 32-bit mode. The second is for 64-bit mode.

8. This opcode is used as a REX prefix in 64-bit mode.

286 Instruction Latencies Appendix C