Appendix C Instruction Latencies 285
Software Optimization Guide for AMD64 Processors
25112 Rev. 3.06 September 2005
JMP mem16:16/32 (far, indirect, call gate) FFh mm-101-xxx VectorPath 123
JMP pntr16:16/32 (far, direct, no call gate) EAh VectorPath 31
JMP pntr16:16/32 (far, direct, call gate) EAh VectorPath 120
JNE/JNZ disp8 75h DirectPath 1 1
JNE/JNZ disp16/32 0Fh 85h DirectPath 1 1
JNO disp8 71h DirectPath 1 1
JNO disp16/32 0Fh 81h DirectPath 1 1
JNP/JPO disp8 7Bh DirectPath 1 1
JNP/JPO disp16/32 0Fh 8Bh DirectPath 1 1
JNS disp8 79h DirectPath 1 1
JNS disp16/32 0Fh 89h DirectPath 1 1
JO disp8 70h DirectPath 1 1
JO disp16/32 0Fh 80h DirectPath 1 1
JP/JPE disp8 7Ah DirectPath 1 1
JP/JPE disp16/32 0Fh 8Ah DirectPath 1 1
JS disp8 78h DirectPath 1 1
JS disp16/32 0Fh 88h DirectPath 1 1
LAHF 9Fh VectorPath 3
LAR reg16/32/64, mreg16/32/64 0Fh 02h 11-xxx-xxx VectorPath 22
LAR reg16/32/64, mem16/32/64 0Fh 02h mm-xxx-xxx VectorPath 24
LDS reg16/32, mem16:16/32 C5h mm-xxx-xxx VectorPath ~
LEA reg16, mem16/32/64 8Dh mm-xxx-xxx VectorPath 3
LEA reg32/64, mem16/32/64 8Dh mm-xxx-xxx DirectPath 1/2 4
LEAVE (16 bit stack size) C9h VectorPath 3
Table 13. Integer Instructions (Continued)
Syntax
Encoding
Decode
type Latency Note
First
byte
Second
byte
ModRM
byte
Notes:
1. Static timing assumes a predicted branch.
2. Store operation also updates ESP—the new register value is available one clock earlier than the specified
latency.
3. The clock count, regardless of the number of shifts or rotates, as determined by CL or imm8.
4. LEA instructions have a latency of 1 when there are two source operands (as in the case of the base + index
form LEA EAX, [EDX+EDI]). Forms with a scale or more than two source operands will have a latency of 2 (LEA
EAX, [EBX+EBX*8]).
5. These instructions have an effective latency as shown. They map to internal NOPs that can be issued at a rate of
three per cycle but do not occupy execution resources.
6. The latency of repeated string instructions can be found in “Latency of Repeated String Instructions” on
page 167.
7. The first latency value is for 32-bit mode. The second is for 64-bit mode.
8. This opcode is used as a REX prefix in 64-bit mode.