AMD 250 manual SSE3 Instructions, 342

Software Optimization Guide for AMD64 Processors 25112 Rev. 3.06 September 2005

C.9	SSE3 Instructions
Table 20.	SSE3 Instructions
			Encoding					Latency	Throughput
Syntax						Decode	FPU
		Prefix	First	2nd
					ModRM byte	type	pipe(s)
		byte	byte	byte
ADDSUBPD xmmreg1,		66h	0Fh	D0h	11-xxx-xxx	Double	FADD	5	1/2
xmmreg2
ADDSUBPD xmmreg,		66h	0Fh	D0h	mm-xxx-xxx	Double	FADD	7	1/2
mem128
ADDSUBPS xmmreg1,		F2h	0Fh	D0h	11-xxx-xxx	Double	FADD	5	1/2
xmmreg2
ADDSUBPS xmmreg,		F2h	0Fh	D0h	mm-xxx-xxx	Double	FADD	7	1/2
mem128
FISTTP [mem16int]			DF		mm-010-xxx	DirectPath	FSTORE	4
FISTTP [mem32int]			DB		mm-010-xxx	DirectPath	FSTORE	4
FISTTP [mem64int]			DD		mm-010-xxx	DirectPath	FSTORE	4
HADDPD xmmreg1,		66h	0Fh	7Ch	11-xxx-xxx	Double	FADD	5	1/2
xmmreg2
HADDPD xmmreg,		66h	0Fh	7Ch	mm-xxx-xxx	VectorPath	FADD	6	1/2
mem128
HADDPS xmmreg1,		F2h	0Fh	7Ch	11-xxx-xxx	Double	FADD	5	1/2
xmmreg2
HADDPS xmmreg1,		F2h	0Fh	7Ch	mm-xxx-xxx	VectorPath	FADD	6	1/2
mem128
HSUBPD xmmreg1,		66h	0Fh	7Dh	11-xxx-xxx	Double	FADD	5	1/2
xmmreg2
HSUBPD xmmreg1,		66h	0Fh	7Dh	mm-xxx-xxx	VectorPath	FADD	6	1/2
mem128
HSUBPS xmmreg1,		F2h	0Fh	7Dh	11-xxx-xxx	Double	FADD	5	1/2
xmmreg2
HSUBPS xmmreg,		F2h	0Fh	7Dh	mm-xxx-xxx	VectorPath	FADD	6	1/2
mem128
LDDQU xmmreg,		F2	0F	F0	mm-xxx-xxx	VectorPath		7	1/2
mem128
MOVDDUP xmmreg1,		F2h	0Fh	12h	11-xxx-xxx	Double	FMUL	2	1/2
xmmreg2
MOVDDUP xmmreg1,		F2h	0Fh	12h	mm-xxx-xxx	Double	FMUL	4	1/2
mem64
MOVSHDUP xmmreg1,		F3h	0Fh	16h	11-xxx-xxx	Double	FMUL	3	1/2
xmmreg2

342 Instruction Latencies Appendix C