AMD 250 manual Integer Instructions, 273, Aaa, Aas

25112 Rev. 3.06 September 2005 Software Optimization Guide for AMD64 Processors

C.2	Integer Instructions
Table 13.	Integer Instructions
			Encoding		Decode
Syntax						Latency	Note
		First	Second	ModRM
					type
		byte	byte	byte
AAA		37h			VectorPath	5
AAD (or directly coded D5 ib, where ib is a byte		D5h	0Ah		VectorPath	5
value other than 0Ah)
AAM (or directly coded D4 ib, where ib is a		D4h	0Ah		VectorPath	15
byte value other than 0Ah)
AAS		3Fh			VectorPath	5
ADC mreg8, reg8		10h		11-xxx-xxx	DirectPath	1
ADC mem8, reg8		10h		mm-xxx-xxx	DirectPath	4
ADC mreg16/32/64, reg16/32/64		11h		11-xxx-xxx	DirectPath	1
ADC mem16/32/64, reg16/32/64		11h		mm-xxx-xxx	DirectPath	4
ADC reg8, mreg8		12h		11-xxx-xxx	DirectPath	1
ADC reg8, mem8		12h		mm-xxx-xxx	DirectPath	4
ADC reg16/32/64, mreg16/32/64		13h		11-xxx-xxx	DirectPath	1
ADC reg16/32/64, mem16/32/64		13h		mm-xxx-xxx	DirectPath	4
ADC AL, imm8		14h			DirectPath	1
ADC AX, imm16		15h			DirectPath	1
ADC EAX, imm32		15h			DirectPath	1
ADC RAX, imm32 (sign extended)		15h			DirectPath	1
ADC mreg8, imm8		80h		11-010-xxx	DirectPath	1
ADC mem8, imm8		80h		mm-010-xxx	DirectPath	4
ADC mreg16/32/64, imm16/32		81h		11-010-xxx	DirectPath	1
ADC mem16/32/64, imm16/32		81h		mm-010-xxx	DirectPath	4
Notes:
1. Static timing assumes a predicted branch.
2. Store operation also updates ESP—the new register value is available one clock earlier than the specified
latency.
3. The clock count, regardless of the number of shifts or rotates, as determined by CL or imm8.
4. LEA instructions have a latency of 1 when there are two source operands (as in the case of the base + index
form LEA EAX, [EDX+EDI]). Forms with a scale or more than two source operands will have a latency of 2 (LEA
EAX, [EBX+EBX*8]).
5. These instructions have an effective latency as shown. They map to internal NOPs that can be issued at a rate of
three per cycle but do not occupy execution resources.
6. The latency of repeated string instructions can be found in “Latency of Repeated String Instructions” on
page 167.
7. The first latency value is for 32-bit mode. The second is for 64-bit mode.
8. This opcode is used as a REX prefix in 64-bit mode.

Appendix C Instruction Latencies 273