Parameter Min Max Unit Memory Read | Analog Devices ADSP-2181

ADSP-2181/ADSP-2183

ADSP-2181

Parameter

Min

Max

Unit

Memory Read

Timing Requirements:

tRDD

RD

Low to Data Valid

0.5tCK – 9 + w

ns

tAA

A0-A13,

xMS

to Data Valid

0.75tCK – 10.5 + w

ns

tRDH

Data Hold from RD High

0

ns

Switching Characteristics:

tRP

RD

Pulse Width

0.5tCK – 5 + w

ns

tCRD

CLKOUT High to

RD

Low

0.25tCK – 5

0.25tCK + 7

ns

tASR

A0-A13,

xMS

Setup before

RD

Low

0.25tCK – 6

ns

tRDA

A0-A13,

xMS

Hold after

RD

Deasserted

0.25tCK – 3

ns

tRWR

RD High to RD or WR Low

0.5tCK – 5

ns

ADSP-2183

28.8 MHz

Parameter

Min

Max

Unit

Memory Read

Timing Requirements:

tRDD

RD

Low to Data Valid

0.5tCK – 9 + w

ns

tAA

A0-A13,

xMS

to Data Valid

0.75tCK – 12.5 + w

ns

tRDH

Data Hold from

RD

High

0

ns

Switching Characteristics:

tRP

RD

Pulse Width

0.5tCK – 5 + w

ns

tCRD

CLKOUT High to

RD

Low

0.25tCK – 5

0.25tCK + 7

ns

tASR

A0-A13, xMS Setup before

RD

Low

0.25tCK – 6

ns

tRDA

A0-A13,

xMS

Hold after

RD

Deasserted

0.25tCK – 3

ns

tRWR

RD

High to

RD

or

WR

Low

0.5tCK – 5

ns

w = wait states x tCK

xMS = PMS, DMS, CMS, IOMS, BMS

CLKOUT

A0 – A13

DMS, PMS,

BMS, IOMS,

CMS

RD

tASR

tCRD tRP

D

tRDD

tAA

tRDA

tRWR

tRDH

WR

Figure 25. Memory Read

REV. 0

–23–

Image 23

Analog Devices ADSP-2181, ADSP-2183 manual MHz Parameter Min Max Unit Memory Read

Contents

General Description Functional Block Diagram Architecture Overview ADSP-2181/ADSP-2183 ADSP-2181/ADSP-2183 Integration PIN Descriptions Pin Input Names Pins Output Function Lowest Priority Interrupt VectorSource of Interrupt Address Hex Highest Priority ADSP-2181 ADSP-2183 System Interface Memory A13 A120 Pmovlay Memory Space Word Size Alignment Address Range Wait State RegisterInternal Idma Port Booting Booting Method Designing AN EZ-ICE-COMPATIBLE System Syntax IOaddr = dreg dreg = IOaddrBiased Rounding Instruction SET Description PM, DM, BM, IOM, & CM Reset GND Grades Parameter Test Conditions Min Max Unit Grade Parameter Min Max Unit ESD Sensitivity Memory Timing SpecificationsFrequency Dependency for Timing Specifications Absolute Maximum Ratings 41C/W 10C/W 31C/W Package50C/W 2C/W 48C/W Test Conditions Capacitive Loading ADSP-2183-SPECIFICATIONS ADSP-2183 Timing Parameters Tqfp Delay Valid Output 28.8 MHz Parameter Min Max Clock Signals and Reset Parameter Min Max Unit Clock Signals and ResetControl Signals Flag Output Hold after Clkout Low5 5tCK FI, or PFx Setup before Clkout Low1, 2, 3 25tCK + IRQxFlag Output Delay from Clkout Low5 25tCK + Parameter Min Max Unit Interrupts and Flag Parameter Min Max Unit Bus Request/Grant 28.8 MHz Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch Parameter Min Max Idma Write, Short Write Cycle Parameter Min Max Unit Idma Write, Short Write Cycle28.8 MHz Parameter Min Max Unit Idma Write, Long Write Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Long Read Cycle Parameter Min Max Unit Idma Read, Long Read Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Short Read Cycle Parameter Min Max Unit Idma Read, Short Read Cycle Lead Tqfp Package Pinout Number Name Pin Outline Dimensions Millimeters Inches Symbol MIN TYP MAX Lead Pqfp Package Pinout PF0 160 Ordering Guide Page Page C2144-16-6/96