Lead Pqfp Package Pinout | Analog Devices ADSP-2183, ADSP-2181

ADSP-2181/ADSP-2183

128-Lead PQFP Package Pinout

PF3

PF2

PF1

128

1

PF0

WR

RD

IOMS

BMS

DMS

CMS

GND

VDD

PMS

A0

A1

A2

A3

A4

A5

A6

A7

XTAL

CLKIN

GND

CLKOUT

GND

VDD

A8

A9

A10

A11

A12

A13

IRQE

MMAP

32

33

IAL IS GND PF4

PF5

PF6 PF7 IAD0 IAD1 IAD2 IAD3 IAD4 IAD5 GND

V

IAD6 IAD7

DD

128L PQFP

(28mm x 28mm)

TOP VIEW

(PINS DOWN)

IAD8

IAD9

IAD10 IAD11 IAD12 IAD13 IAD14 IAD15 IRD IWR GND D23

97

96

65

64

D22

D21

D20

D19

D18

D17

D16

D15 GND VDD GND D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 GND D4 D3 D2 D1 D0

VDD

BG

EBG

BR

EBR

PWD	IRQ2 BMODE PWDACK IACK	BGH	V	GND	IRQL0	IRQL1 FL0 FL1 FL2	DT0 TFS0 RFS0 DR0 SCLK0 DT1/F0	IRQ1 TFS1/	IRQ0 RFS1/ GND DR1/FI SCLK1 ERESET RESET EMS EE ECLK ELOUT ELIN EINT
			DD

–34–

REV. 0

Image 34

Analog Devices ADSP-2183, ADSP-2181 manual Lead Pqfp Package Pinout

Contents

Functional Block Diagram General Description ADSP-2181/ADSP-2183 Architecture Overview ADSP-2181/ADSP-2183 Integration Pin Input Names Pins Output Function PIN Descriptions Highest Priority Interrupt VectorSource of Interrupt Address Hex Lowest Priority System Interface ADSP-2181 ADSP-2183 Pmovlay Memory A13 A120 Internal Address Range Wait State RegisterMemory Space Word Size Alignment Booting Method Idma Port Booting Instruction SET Description Syntax IOaddr = dreg dreg = IOaddrBiased Rounding Designing AN EZ-ICE-COMPATIBLE System Reset GND PM, DM, BM, IOM, & CM Grade Parameter Min Max Unit Grades Parameter Test Conditions Min Max Unit Absolute Maximum Ratings Memory Timing SpecificationsFrequency Dependency for Timing Specifications ESD Sensitivity 50C/W 2C/W 48C/W Package41C/W 10C/W 31C/W Capacitive Loading Test Conditions ADSP-2183-SPECIFICATIONS ADSP-2183 Timing Parameters Tqfp Delay Valid Output Control Signals Parameter Min Max Unit Clock Signals and Reset28.8 MHz Parameter Min Max Clock Signals and Reset Parameter Min Max Unit Interrupts and Flag FI, or PFx Setup before Clkout Low1, 2, 3 25tCK + IRQxFlag Output Delay from Clkout Low5 25tCK + Flag Output Hold after Clkout Low5 5tCK Parameter Min Max Unit Bus Request/Grant Parameter Min Max Unit Memory Read 28.8 MHz Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch 28.8 MHz Parameter Min Max Unit Idma Write, Short Write CycleParameter Min Max Idma Write, Short Write Cycle Parameter Min Max Unit Idma Write, Long Write Cycle Parameter Min Max Unit Idma Read, Long Read Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Long Read Cycle Parameter Min Max Unit Idma Read, Short Read Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Short Read Cycle Lead Tqfp Package Pinout Pin Number Name Millimeters Inches Symbol MIN TYP MAX Outline Dimensions Lead Pqfp Package Pinout PF0 160 Ordering Guide Page Page C2144-16-6/96