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ADSP-2181/ADSP-2183
ADSP-2181
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IDMA Write, Long Write Cycle |
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Timing Requirements: |
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tIKW | IACK | Low before Start of Write1 | 0 |
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tIKSU | IACK | Low2, 3 | 0.5tCK + 10 |
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tIKH | 2 |
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Switching Characteristics: |
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tIKLW | Start of Write to | IACK | Low4 | 1.5tCK |
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tIKHW | Start of Write to IACK High |
| 15 | ns |
ADSP-2183
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| 28.8 MHz |
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Parameter |
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IDMA Write, Long Write Cycle |
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Timing Requirements: |
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tIKW | IACK | Low before Start of Write1 | 0 |
| ns | ||||||
tIKSU | IACK | Low2, 3 | 0.5tCK + 10 |
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tIKH | IACK | Low2, 3 | 2 |
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Switching Characteristics: |
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tIKLW | Start of Write to | IACK | Low4 | 1.5tCK |
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tIKHW | Start of Write to | IACK | High |
| 17 | ns |
NOTES
1Start of Write = IS Low and IWR Low.
2If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH.
3If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH.
4This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the User’s Manual.
| tIKW |
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IACK |
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| tIKHW |
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| tIKLW |
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IS |
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IWR |
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| tIKSU | tIKH |
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IAD |
| DATA |
Figure 30. IDMA Write, Long Write Cycle
REV. 0 |