Manuals / Analog Devices / Computer Equipment / Network Card

Analog Devices ADSP-2181, ADSP-2183 manual Lead Tqfp Package Pinout

Models: ADSP-2183 ADSP-2181

1 40

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Page 31

ADSP-2181/ADSP-2183

128-Lead TQFP Package Pinout

IS

128

1

IAL PF3 PF2 PF1 PF0

WR

RD

IOMS

BMS

DMS

CMS

GND

VDD

PMS

A0

A1

A2

A3

A4

A5

A6

A7

XTAL CLKIN GND CLKOUT

GND

VDD

A8

A9

A10

A11

A12

A13

IRQE

MMAP

PWD

IRQ2

38

39

GND PF4 PF5 PF6 PF7 IAD0 IAD1 IAD2 IAD3 IAD4 IAD5 GND V IAD6 IAD7 IAD8 IAD9	0	1	2	3	4	5	IRD IWR
	AID1	AID1	AID1	AID1	AID1	AID1	IRD IWR
DD

103

102

TOP VIEW

(PINS DOWN)

65 64

GND

D23

D22

D21

D20

D19

D18

D17

D16

D15

GND

VDD

GND

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

GND

D4

D3

D2

D1

D0

VDD

BG

EBG

BR

EBR

EINT

ELIN ELOUT ECLK

BMODE PWDACK	IACK	BGH	V	GND	IRQL0	IRQL1 FL0 FL1 FL2	DT0 TFS0 RFS0 DR0 SCLK0 DT1/F0	TFS1/IRQ1	RFS1/IRQ0 GND DR1/FI SCLK1 ERESET RESET EMS EE
			DD

REV. 0

–31–

Image 31

Analog Devices ADSP-2181, ADSP-2183 manual Lead Tqfp Package Pinout

Contents

General Description Functional Block DiagramArchitecture Overview ADSP-2181/ADSP-2183ADSP-2181/ADSP-2183 Integration PIN Descriptions Pin Input Names Pins Output FunctionLowest Priority Interrupt VectorSource of Interrupt Address Hex Highest PriorityADSP-2181 ADSP-2183 System InterfaceMemory A13 A120 PmovlayInternal Address Range Wait State RegisterMemory Space Word Size Alignment Idma Port Booting Booting MethodDesigning AN EZ-ICE-COMPATIBLE System Syntax IOaddr = dreg dreg = IOaddrBiased Rounding Instruction SET DescriptionPM, DM, BM, IOM, & CM Reset GNDGrades Parameter Test Conditions Min Max Unit Grade Parameter Min Max UnitESD Sensitivity Memory Timing SpecificationsFrequency Dependency for Timing Specifications Absolute Maximum Ratings50C/W 2C/W 48C/W Package41C/W 10C/W 31C/W Test Conditions Capacitive LoadingADSP-2183-SPECIFICATIONS ADSP-2183 Timing Parameters Tqfp Delay Valid Output Control Signals Parameter Min Max Unit Clock Signals and Reset28.8 MHz Parameter Min Max Clock Signals and Reset Flag Output Hold after Clkout Low5 5tCK FI, or PFx Setup before Clkout Low1, 2, 3 25tCK + IRQxFlag Output Delay from Clkout Low5 25tCK + Parameter Min Max Unit Interrupts and FlagParameter Min Max Unit Bus Request/Grant 28.8 MHz Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory ReadParameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch 28.8 MHz Parameter Min Max Unit Idma Write, Short Write CycleParameter Min Max Idma Write, Short Write Cycle Parameter Min Max Unit Idma Write, Long Write Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Long Read Cycle Parameter Min Max Unit Idma Read, Long Read Cycle28.8 MHz Parameter Min Max Unit Idma Read, Short Read Cycle Parameter Min Max Unit Idma Read, Short Read CycleLead Tqfp Package Pinout Number Name PinOutline Dimensions Millimeters Inches Symbol MIN TYP MAXLead Pqfp Package Pinout PF0 160 Ordering Guide Page Page C2144-16-6/96