Analog Devices ADSP-2183, ADSP-2181 manual

ADSP-2181/ADSP-2183

ADSP-2181

Parameter			Min	Max	Unit

IDMA Read, Short Read Cycle
Timing Requirements:
tIKR	IACK	Low before Start of Read1	0		ns
tIRP	Duration of Read		15		ns
Switching Characteristics:
tIKHR	IACK	High after Start of Read1		15	ns
tIKDH	IAD15–0 Data Hold after End of Read2		0		ns
tIKDD	IAD15–0 Data Disabled after End of Read2			10	ns
tIRDE	IAD15–0 Previous Data Enabled after Start of Read		0		ns
tIRDV	IAD15–0 Previous Data Valid after Start of Read			15	ns

ADSP-2183

			28.8 MHz
Parameter			Min	Max	Unit

IDMA Read, Short Read Cycle
Timing Requirements:
tIKR	IACK	Low before Start of Read1	0		ns
tIRP	Duration of Read		15		ns
Switching Characteristics:
tIKHR	IACK	High after Start of Read1		17	ns
tIKDH	IAD15–0 Data Hold after End of Read2		0		ns
tIKDD	IAD15–0 Data Disabled after End of Read2			10	ns
tIRDE	IAD15–0 Previous Data Enabled after Start of Read		0		ns
tIRDV	IAD15–0 Previous Data Valid after Start of Read			15	ns

NOTES

1Start of Read = IS Low and IRD Low.

2End of Read = IS High or IRD High.

IACK

tIKR

tIKHR

IS

IRD

tIRDE

IAD 15–0

tIRDV

tIRP

PREVIOUS

DATA

tIKDH

tIKDD

Figure 32. IDMA Read, Short Read Cycle

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Image 30

Analog Devices ADSP-2183, ADSP-2181 manual Parameter Min Max Unit Idma Read, Short Read Cycle

Contents

Functional Block Diagram General Description ADSP-2181/ADSP-2183 Architecture Overview ADSP-2181/ADSP-2183 Integration Pin Input Names Pins Output Function PIN Descriptions Highest Priority Interrupt VectorSource of Interrupt Address Hex Lowest Priority System Interface ADSP-2181 ADSP-2183 Pmovlay Memory A13 A120 Address Range Wait State Register InternalMemory Space Word Size Alignment Booting Method Idma Port Booting Instruction SET Description Syntax IOaddr = dreg dreg = IOaddrBiased Rounding Designing AN EZ-ICE-COMPATIBLE System Reset GND PM, DM, BM, IOM, & CM Grade Parameter Min Max Unit Grades Parameter Test Conditions Min Max Unit Absolute Maximum Ratings Memory Timing SpecificationsFrequency Dependency for Timing Specifications ESD Sensitivity Package 50C/W 2C/W 48C/W41C/W 10C/W 31C/W Capacitive Loading Test Conditions ADSP-2183-SPECIFICATIONS ADSP-2183 Timing Parameters Tqfp Delay Valid Output Parameter Min Max Unit Clock Signals and Reset Control Signals28.8 MHz Parameter Min Max Clock Signals and Reset Parameter Min Max Unit Interrupts and Flag FI, or PFx Setup before Clkout Low1, 2, 3 25tCK + IRQxFlag Output Delay from Clkout Low5 25tCK + Flag Output Hold after Clkout Low5 5tCK Parameter Min Max Unit Bus Request/Grant Parameter Min Max Unit Memory Read 28.8 MHz Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch Parameter Min Max Unit Idma Write, Short Write Cycle 28.8 MHzParameter Min Max Idma Write, Short Write Cycle Parameter Min Max Unit Idma Write, Long Write Cycle Parameter Min Max Unit Idma Read, Long Read Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Long Read Cycle Parameter Min Max Unit Idma Read, Short Read Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Short Read Cycle Lead Tqfp Package Pinout Pin Number Name Millimeters Inches Symbol MIN TYP MAX Outline Dimensions Lead Pqfp Package Pinout PF0 160 Ordering Guide Page Page C2144-16-6/96