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Analog Devices ADSP-2181, ADSP-2183 manual Parameter Min Max Unit Serial Ports

Models: ADSP-2183 ADSP-2181

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ADSP-2181/ADSP-2183

ADSP-2181/ADSP-2183

Parameter		Min	Max	Unit

Serial Ports
Timing Requirements:
tSCK	SCLK Period	50		ns
tSCS	DR/TFS/RFS Setup before SCLK Low	4		ns
tSCH	DR/TFS/RFS Hold after SCLK Low	7		ns
tSCP	SCLKIN Width	20		ns
Switching Characteristics:
tCC	CLKOUT High to SCLKOUT	0.25tCK	0.25tCK + 10	ns
tSCDE	SCLK High to DT Enable	0		ns
tSCDV	SCLK High to DT Valid		15	ns
tRH	TFS/RFSOUT Hold after SCLK High	0		ns
tRD	TFS/RFSOUT Delay from SCLK High		15	ns
tSCDH	DT Hold after SCLK High	0		ns
tTDE	TFS (Alt) to DT Enable	0		ns
tTDV	TFS (Alt) to DT Valid		14	ns
tSCDD	SCLK High to DT Disable		15	ns
tRDV	RFS (Multichannel, Frame Delay Zero) to DT Valid		15	ns

CLKOUT

SCLK

DR

TFSIN

RFSIN

RFSOUT

TFSOUT

DT

TFS

ALTERNATE

FRAME MODE

RFS

MULTICHANNEL MODE, FRAME DELAY 0 (MFD = 0)

tCC

tRD

tRH

tSCDV

tSCDE

tTDE

tTDV

tRDV

tCC

tSCS tSCH

tSCDH

tSCK

tSCP

tSCP

tSCDD

Figure 27. Serial Ports

REV. 0

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Analog Devices ADSP-2181, ADSP-2183 manual Parameter Min Max Unit Serial Ports

Contents

General Description Functional Block DiagramArchitecture Overview ADSP-2181/ADSP-2183ADSP-2181/ADSP-2183 Integration PIN Descriptions Pin Input Names Pins Output FunctionSource of Interrupt Address Hex Interrupt VectorHighest Priority Lowest PriorityADSP-2181 ADSP-2183 System InterfaceMemory A13 A120 PmovlayInternal Address Range Wait State RegisterMemory Space Word Size Alignment Idma Port Booting Booting MethodBiased Rounding Syntax IOaddr = dreg dreg = IOaddrInstruction SET Description Designing AN EZ-ICE-COMPATIBLE SystemPM, DM, BM, IOM, & CM Reset GNDGrades Parameter Test Conditions Min Max Unit Grade Parameter Min Max UnitFrequency Dependency for Timing Specifications Memory Timing SpecificationsAbsolute Maximum Ratings ESD Sensitivity50C/W 2C/W 48C/W Package41C/W 10C/W 31C/W Test Conditions Capacitive LoadingADSP-2183-SPECIFICATIONS ADSP-2183 Timing Parameters Tqfp Delay Valid Output Control Signals Parameter Min Max Unit Clock Signals and Reset28.8 MHz Parameter Min Max Clock Signals and Reset Flag Output Delay from Clkout Low5 25tCK + FI, or PFx Setup before Clkout Low1, 2, 3 25tCK + IRQxParameter Min Max Unit Interrupts and Flag Flag Output Hold after Clkout Low5 5tCKParameter Min Max Unit Bus Request/Grant 28.8 MHz Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory ReadParameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch 28.8 MHz Parameter Min Max Unit Idma Write, Short Write CycleParameter Min Max Idma Write, Short Write Cycle Parameter Min Max Unit Idma Write, Long Write Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Long Read Cycle Parameter Min Max Unit Idma Read, Long Read Cycle28.8 MHz Parameter Min Max Unit Idma Read, Short Read Cycle Parameter Min Max Unit Idma Read, Short Read CycleLead Tqfp Package Pinout Number Name PinOutline Dimensions Millimeters Inches Symbol MIN TYP MAXLead Pqfp Package Pinout PF0 160 Ordering Guide Page Page C2144-16-6/96