ADSP-2181/ADSP-2183
ADSP-2181/ADSP-2183
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| Min | Max | Unit |
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Bus Request/Grant |
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Timing Requirements: |
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tBH |
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| Hold after CLKOUT High1 | 0.25tCK + 2 |
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BR |
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tBS | BR |
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| Setup before CLKOUT Low1 | 0.25tCK + 17 |
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Switching Characteristics: |
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tSD | CLKOUT High to | xMS | , |
| 0.25tCK + 10 | ns | ||||||||||||||||||
| RD | , |
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| WR | Disable |
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tSDB | xMS | , | RD | , |
| WR |
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| Disable to BG Low | 0 |
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tSE | BG | High to | xMS | , |
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| RD | , |
| WR | Enable | 0 |
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tSEC | xMS, RD, WR |
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tSDBH | Enable to CLKOUT High | 0.25tCK – 7 |
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xMS | , | RD | , |
| WR |
| Low2 |
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| Disable to | BGH | 0 |
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tSEH | BGH | High to | xMS | , |
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| RD | , | WR | Enable2 | 0 |
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NOTES
xMS = PMS, DMS, CMS, IOMS, BMS
1BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. Refer to the
2BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
CLKOUT
BR
CLKOUT
PMS, DMS
BMS, RD WR
BG
BGH
tBH
tBS
tSD
tSDB
tSDBH
tSE
tSEC
tSEH
Figure 24. Bus Request–Bus Grant
REV. 0 |
