Manuals / Analog Devices / Computer Equipment / Network Card

Analog Devices ADSP-2183, ADSP-2181 manual Parameter Min Max Unit Memory Write

Models: ADSP-2183 ADSP-2181

1 40

Download 40 pages 6.22 Kb

Page 24

ADSP-2181/ADSP-2183

ADSP-2181/ADSP-2183

Parameter

Min

Max

Unit

Memory Write

Switching Characteristics:

tDW

Data Setup before

WR

High

0.5tCK – 7+ w

ns

tDH

Data Hold after WR High

0.25tCK – 2

ns

tWP

WR

Pulse Width

0.5tCK – 5 + w

ns

tWDE

WR

Low to Data Enabled

0

ns

tASW

A0-A13,

xMS

Setup before

WR

Low

0.25tCK – 6

ns

tDDR

Data Disable before

WR

or

RD

Low

0.25tCK – 7

ns

tCWR

CLKOUT High to

WR

Low

0.25tCK – 5

0.25 tCK + 7

ns

tAW

A0-A13, xMS, Setup before

WR

Deasserted

0.75tCK – 9 + w

ns

tWRA

A0-A13,

xMS

Hold after

WR

Deasserted

0.25tCK – 3

ns

tWWR

WR

High to

RD

or

WR

Low

0.5tCK – 5

ns

w = wait states x tCK

xMS = PMS, DMS, CMS, IOMS, BMS

CLKOUT

A0–A13

DMS, PMS,

BMS, CMS,

IOMS

WR

D

tASW

tCWR

tWRA

tWWR

tWP

tAW

tDH

tDDR

tDW tWDE

RD

Figure 26. Memory Write

–24–

REV. 0

Image 24

Analog Devices ADSP-2183, ADSP-2181 manual Parameter Min Max Unit Memory Write

Contents

Functional Block Diagram General DescriptionADSP-2181/ADSP-2183 Architecture OverviewADSP-2181/ADSP-2183 Integration Pin Input Names Pins Output Function PIN DescriptionsInterrupt Vector Source of Interrupt Address HexHighest Priority Lowest PrioritySystem Interface ADSP-2181 ADSP-2183Pmovlay Memory A13 A120Address Range Wait State Register InternalMemory Space Word Size Alignment Booting Method Idma Port BootingSyntax IOaddr = dreg dreg = IOaddr Biased RoundingInstruction SET Description Designing AN EZ-ICE-COMPATIBLE SystemReset GND PM, DM, BM, IOM, & CMGrade Parameter Min Max Unit Grades Parameter Test Conditions Min Max UnitMemory Timing Specifications Frequency Dependency for Timing SpecificationsAbsolute Maximum Ratings ESD SensitivityPackage 50C/W 2C/W 48C/W41C/W 10C/W 31C/W Capacitive Loading Test ConditionsADSP-2183-SPECIFICATIONS ADSP-2183 Timing Parameters Tqfp Delay Valid Output Parameter Min Max Unit Clock Signals and Reset Control Signals28.8 MHz Parameter Min Max Clock Signals and Reset FI, or PFx Setup before Clkout Low1, 2, 3 25tCK + IRQx Flag Output Delay from Clkout Low5 25tCK +Parameter Min Max Unit Interrupts and Flag Flag Output Hold after Clkout Low5 5tCKParameter Min Max Unit Bus Request/Grant Parameter Min Max Unit Memory Read 28.8 MHz Parameter Min Max Unit Memory ReadParameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch Parameter Min Max Unit Idma Write, Short Write Cycle 28.8 MHzParameter Min Max Idma Write, Short Write Cycle Parameter Min Max Unit Idma Write, Long Write Cycle Parameter Min Max Unit Idma Read, Long Read Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Long Read CycleParameter Min Max Unit Idma Read, Short Read Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Short Read CycleLead Tqfp Package Pinout Pin Number NameMillimeters Inches Symbol MIN TYP MAX Outline DimensionsLead Pqfp Package Pinout PF0 160 Ordering Guide Page Page C2144-16-6/96