Belkin PM11-EC/RAMA, PM11-EL/RAMA Dram Clock, Dram Timing, Sdram CAS Latency, Bank Interleave

Models: PM11-EC/RAMA PM11-EL/RAMA PM11-UL/RAMA

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Award BIOS Setup Utility

DRAM Clock

This field is used to select the clock speed of the DIMM.

By SPD The EEPROM on a DIMM has SPD (Serial Presence Detect) data structure that stores information about the module such as the memory type, memory size, memory speed, etc. When this option is selected, the system will run according to the information in the EEPROM.

100 MHz The memory clock speed will run at 200MHz.

133 MHz The memory clock speed will run at 266MHz.

DRAM Timing

This field is used to select the timing of the DRAM.

By SPD The EEPROM on a DIMM has SPD (Serial Presence Detect) data structure that stores information about the module such as the memory type, memory size, memory speed, etc. When this option is selected, the system will run according to the information in the EEPROM.

Manual It allows you to configure the fields that follow. The system will run according to the settings in these fields.

SDRAM CAS Latency

The default setting is 3 which is 3 clock cycles for the CAS latency.

Bank Interleave

The options are 2 Bank, 4 Bank and Disabled.

Precharge to Active (Trp)

The options are 2T and 3T.

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Image 65
Belkin PM11-EC/RAMA, PM11-EL/RAMA Dram Clock, Dram Timing, Sdram CAS Latency, Bank Interleave, Precharge to Active Trp