Belkin PM11-UL/RAMA manual AGP Master 1 WS Read, CPU to PCI Write Buffer, PCI Master 0 WS Write

Award BIOS Setup Utility

AGP Master 1 WS Read

Set this field to Enabled to add one clock tick to AGP read operations.

CPU & PCI Bus Control

Move the cursor to this field and press <Enter>. The following fields will appear

CPU to PCI Write Buffer

Enabled Writes from the CPU to the PCI bus are buffered to offset the speed difference between the CPU and PCI bus.

Disabled Writes are not buffered therefore the CPU must wait until the write cycle is complete before starting another write cycle.

PCI Master 0 WS Write

When enabled, writes to the PCI bus are executed with zero wait state.

PCI Delay Transaction

When enabled, this function frees up the PCI bus for other PCI masters during the PCI-to-ISA transactions. This allows PCI and ISA buses to be used more efficiently and prevents degradation of performance on the PCI bus when ISA accesses are made.

Memory Hole

This field is used to select the memory area that must not be addressed to the ISA bus.

System BIOS Cacheable

When this field is enabled, accesses to the system BIOS ROM addressed at F0000H-FFFFFH are cached, provided that the cache controller is enabled. The larger the range of the Cache RAM, the higher the efficiency of the system.

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