PRELIMINARY CY8CNP102B, CY8CNP102E
AC Electrical Characteristics
The following AC electrical specifications list the guaranteed maximum and minimum specifications for the voltage and temperature range: 3.0V to 3.6V over the temperature range of
AC Chip Level Specifications
Table 14. 3.3V AC Chip Level Specifications (CY8CNP102B)
Symbol | Description | Min | Typ | Max | Units | Notes |
FIMO24 | Internal Main Oscillator Frequency for | 23.4 | 24 | 24.6[4, 5, 6] | MHz | Trimmed for 3.3V operation using |
| 24 MHz |
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| factory trim values. See the figure |
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| on page 10. SLIMO Mode = 0. |
FIMO6 | Internal Main Oscillator Frequency for | 5.75 | 6 | 6.35[4 , 5, 6] | MHz | Trimmed for 3.3V operation using |
| 6 MHz |
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| factory trim values. See the figure |
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| on page 10. |
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| SLIMO Mode = 1. |
FCPU2 | CPU Frequency (3.3V Nominal) | 0.93 | 12 | 12.3[5, 6] | MHz |
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F48M | Digital PSoC Block Frequency | 0 | 48 | 49.2[4, 5, 7] | MHz | Refer to section AC Digital Block |
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| Specifications on page 19. |
F24M | Digital PSoC Block Frequency | 0 | 24 | 24.6[5, 7] | MHz |
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F32K1 | Internal Low Speed Oscillator Frequency | 15 | 32 | 64 | kHz |
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F32K2 | External Crystal Oscillator | – | 32.768 | – | kHz | Accuracy is capacitor and crystal |
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| dependent. 50% duty cycle. |
FPLL | PLL Frequency | – | 23.986 | – | MHz | A multiple (x732) of crystal |
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| frequency. |
Jitter24M2 | 24 MHz Period Jitter (PLL) | – | – | 600 | ps |
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TPLLSLEW | PLL Lock Time | 0.5 | – | 10 | ms |
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TPLLSLEWLOW | PLL Lock Time for Low Gain Setting | 0.5 | – | 50 | ms |
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TOS | External Crystal Oscillator Startup to 1% | – | 250 | 500 | ms |
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TOSACC | External Crystal Oscillator Startup to | – | 300 | 600 | ms | The crystal oscillator frequency is |
| 100 ppm |
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| within 100 ppm of its final value |
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| by the end of the Tosacc period. |
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| Correct operation assumes a |
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| properly loaded 1 uW maximum |
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| drive level 32.768 kHz crystal. |
Jitter32k | 32 kHz Period Jitter | – | 100 |
| ns |
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TXRST | External Reset Pulse Width | 10 | – | – | μs |
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DC24M | 24 MHz Duty Cycle | 40 | 50 | 60 | % |
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Step24M | 24 MHz Trim Step Size | – | 50 | – | kHz |
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Fout48M | 48 MHz Output Frequency | 46.8 | 48.0 | 49.2[4,6] | MHz | Trimmed. Using factory trim |
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| values. |
Jitter24M1 | 24 MHz Period Jitter (IMO) | – | 600 |
| ps |
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FMAX | Maximum frequency of signal on row input | – | – | 12.3 | MHz |
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| or row output. |
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TRAMP | Supply Ramp Time | 0 | – | – | μs |
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Notes
4.4.75V < Vcc < 5.25V.
5.Accuracy derived from Internal Main Oscillator with appropriate trim for Vcc range.
6.3.0V < Vcc < 3.6V. See Application Note AN2012 “Adjusting PSoC Micro controller Trims for Dual
7.See individual user module data sheets for information on maximum frequencies for user modules.
Document #: | Page 17 of 38 |
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