Package Diagrams, Thermal Impedance, Tqfp

PRELIMINARY CY8CNP102B, CY8CNP102E

Packaging Information

This section describes the packaging specifications for the PSoC NV device and the thermal impedances for TQFP package.

Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tool dimensions, refer to the document “PSoC Emulator Pod Dimensions” at http://www.cypress.com/design/MR10161.

Package Diagrams

Figure 15. 100-Pin TQFP - 14 x 14 x 1.4 mm

51-85048 *C

Thermal Impedance

Table 41. Thermal Impedance

Package[10]	Typical θJA *	Typical θJC *
100 TQFP	26.14 oC/W	5.81 oC/W

Note

10. * TJ = TA + POWER x θJA

Document #: 001-43991 Rev. *D

Page 36 of 38

[+] Feedback

Page 36

Image 36

Cypress CY8CNP102E, CY8CNP102B manual Package Diagrams, Thermal Impedance, Tqfp, 81 oC/W

Contents

Features Overview Logic Block Diagram Pinouts GpioENW NVW NVA1NVA2 ENA1 PSoC NV Functional Overview PSoC NV CoreNvSRAM Data Memory NvSRAM Operation Programmable Digital System Programmable Analog SystemAdditional System Resources Development Tools PSoC Designer Software SubsystemsEsigner Designing with User Modules Hardware ToolsUser Module and Source Code Development Flows Cypress nvSRAM user Module Parts per millionMicrohenry Picosecond Microsecond Samples per second Operating Temperature 3V OperationAbsolute Maximum Ratings ESD DC Electrical Characteristics Cmrroa Psrroa Psrr OB DC Analog Reference Specifications Capacitor Unit Value Switch CapAgnd = BandGap1 Agnd = 1.6 x BandGap1 Resistor Unit Value Continuous Time Vdd Value for Ppor Trip positive ramp PORLEV10 = 00b Vdd Value for Ppor Trip negative rampPORLEV10 = 00b Ppor Hysteresis PORLEV10 = 00b Supply Current During Programming or Verify Input Low Voltage During Programming or VerifyDriving internal pull During Programming or Verify Down resistor AC Electrical Characteristics DC24M Power Up Recall Duration Gpio Operating Frequency 12.3 MHz Normal Strong Mode TRiseSStore Cycle Duration 12.5 Low Voltage Trigger Level Bwoa Crcprs SpimSpis Bwob Data Set up Time to Falling Edge of Sclk Data Out Delay from Falling Edge of Sclk 0V ≤ Vcc ≤Setup Time for a Repeated Start Condition Data Hold Time Data Setup Time 5V Operation Capacitive Load on Pins as Input Pin dependent. Temp = 25oC High Output Level VccCombined IOH budget Input Low Level 75 to Input Leakage Current Port 0 Analog Pins Gross tested to 1 μA Input Capacitance Port 0 Analog PinsLow power comparator LPC reference voltage range Vcc Average Input Offset Voltage Drift Psrrob PORLEV10 = 10b Vdd Value for Ppor Trip negative ramp PORLEV10 = 10b Ppor HysteresisVM20 = 011b VM20 = 100b Output Low Voltage During Programming or VerifyBlock Using factory trim values MHz Trimmed for 5V operationSee on Internal Main Oscillator Frequency for 6 MHz MHz Normal Strong Mode TRiseF Gpio Operating FrequencyVcc = 4.75V to TFallF Maximum Frequency 49.2 MHz 75V ≤ Vcc ≤ Maximum Input Clock Frequency 24.6 MHz 75V ≤ Vcc ≤ CRC Mode MHz due to 2 Over clockingSions Transmitter Maximum Input Clock Frequency 24.6 MHz Vcc ≥ 4.75V, 2 Stop Bits MHz due to 8 Over clocking 49.2 Data Out Delay from Falling Edge of Sclk 75V ≤ Vcc ≤ Switching Waveforms A b l e External Crystal Oscillator Startup Timing Diagram L e c t Part Numbering Nomenclature Ordering InformationCY8CNP102B-AXI CY8CNP102E-AXI Package Diagrams Thermal ImpedanceTqfp 81 oC/W Document History PyrsGVCH/PYRS Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB

Packaging Information

Package Diagrams

Figure 15. 100-Pin TQFP - 14 x 14 x 1.4 mm

Thermal Impedance

100 TQFP

5.81 oC/W