Cypress CY8CNP102B Rise Time of Sclk, Fall Time of Sclk, Data Set up Time to Falling Edge of Sclk

PRELIMINARY CY8CNP102B, CY8CNP102E

AC Programming Specifications

Table 20. 3.3V AC Programming Specifications (CY8CNP102B)

Symbol	Description	Min	Typ	Max	Units	Notes
TRSCLK	Rise Time of SCLK	1	–	20	ns
TFSCLK	Fall Time of SCLK	1	–	20	ns
TSSCLK	Data Set up Time to Falling Edge of SCLK	40	–	–	ns
THSCLK	Data Hold Time from Falling Edge of SCLK	40	–	–	ns
FSCLK	Frequency of SCLK	0	–	8	MHz
TERASEB	Flash Erase Time (Block)	–	10	–	ms
TWRITE	Flash Block Write Time	–	10	–	ms
TDSCLK3	Data Out Delay from Falling Edge of SCLK	–	–	50	ns	3.0V ≤ Vcc ≤ 3.6V

AC I2C Specifications

Table 21. 3.3V AC Characteristics of the I2C SDA and SCL Pins (CY8CNP102B)

Symbol	Description	Standard Mode		Fast Mode		Units
		Min	Max	Min	Max
FSCLI2C	SCL Clock Frequency	0	100	0	400	kHz
THDSTAI2C	Hold Time (repeated) START Condition. After this period, the	4.0	–	0.6	–	μs
	first clock pulse is generated.
TLOWI2C	LOW Period of the SCL Clock	4.7	–	1.3	–	μs
THIGHI2C	HIGH Period of the SCL Clock	4.0	–	0.6	–	μs
TSUSTAI2C	Setup Time for a Repeated START Condition	4.7	–	0.6	–	μs
THDDATI2C	Data Hold Time	0	–	0	–	μs
T	Data Setup Time	250	–	100[9]	–	ns
SUDATI2C
TSUSTOI2C	Setup Time for STOP Condition	4.0	–	0.6	–	μs
TBUFI2C	Bus Free Time Between a STOP and START Condition	4.7	–	1.3	–	μs
TSPI2C	Pulse Width of spikes are suppressed by the input filter.	–	–	0	50	ns

Note

9. A Fast Mode I2C-bus device may be used in a Standard-Mode I2C-bus system, but the requirement tSUDAT ≥ 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard Mode I2C bus specification) before the SCL line is released.

Document #: 001-43991 Rev. *D Page 21 of 38

[+] Feedback