Rise Time of Sclk | Cypress CY8CNP102E, CY8CNP102B specification

PRELIMINARY CY8CNP102B, CY8CNP102E

AC Programming Specifications

Table 39. 5V AC Programming Specifications (CY8CNP102E)

Symbol	Description	Min	Typ	Max	Units	Notes
TRSCLK	Rise Time of SCLK	1	–	20	ns
TFSCLK	Fall Time of SCLK	1	–	20	ns
TSSCLK	Data Set up Time to Falling Edge of SCLK	40	–	–	ns
THSCLK	Data Hold Time from Falling Edge of SCLK	40	–	–	ns
FSCLK	Frequency of SCLK	0	–	8	MHz
TERASEB	Flash Erase Time (Block)	–	10	–	ms
TWRITE	Flash Block Write Time	–	10	–	ms
TDSCLK	Data Out Delay from Falling Edge of SCLK	–	–	45	ns	4.75V ≤ Vcc ≤ 5.25V
AC I2C Specifications
Table 40. 5V AC Characteristics of the I2C SDA and SCL Pins (CY8CNP102E)

	Symbol	Description	Standard Mode		Fast Mode		Units
	Symbol	Description	Min	Max	Min	Max	Units
			Min	Max	Min	Max
	FSCLI2C	SCL Clock Frequency	0	100	0	400	kHz
	THDSTAI2C	Hold Time (repeated) START Condition. After this	4.0	–	0.6	–	μs
		period, the first clock pulse is generated.
	TLOWI2C	LOW Period of the SCL Clock	4.7	–	1.3	–	μs
	THIGHI2C	HIGH Period of the SCL Clock	4.0	–	0.6	–	μs
	TSUSTAI2C	Setup Time for a Repeated START Condition	4.7	–	0.6	–	μs
	THDDATI2C	Data Hold Time	0	–	0	–	μs
	T	Data Setup Time	250	–	100[9]	–	ns
	SUDATI2C
	TSUSTOI2C	Setup Time for STOP Condition	4.0	–	0.6	–	μs
	TBUFI2C	Bus Free Time Between a STOP and START Condition	4.7	–	1.3	–	μs
	TSPI2C	Pulse Width of spikes are suppressed by the input filter.	–	–	0	50	ns

Document #: 001-43991 Rev. *D

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Cypress CY8CNP102E, CY8CNP102B manual Rise Time of Sclk, Data Out Delay from Falling Edge of Sclk 75V ≤ Vcc ≤

Contents

Features Overview Logic Block Diagram ENW PinoutsGpio NVW NVA1NVA2 ENA1 PSoC NV Functional Overview PSoC NV CoreNvSRAM Data Memory NvSRAM Operation Additional System Resources Programmable Digital SystemProgrammable Analog System Esigner Development ToolsPSoC Designer Software Subsystems User Module and Source Code Development Flows Designing with User ModulesHardware Tools Cypress nvSRAM user Module Parts per millionMicrohenry Picosecond Microsecond Samples per second Operating Temperature 3V OperationAbsolute Maximum Ratings ESD DC Electrical Characteristics Cmrroa Psrroa Psrr OB DC Analog Reference Specifications Capacitor Unit Value Switch CapAgnd = BandGap1 Agnd = 1.6 x BandGap1 Resistor Unit Value Continuous Time Vdd Value for Ppor Trip positive ramp PORLEV10 = 00b Vdd Value for Ppor Trip negative rampPORLEV10 = 00b Ppor Hysteresis PORLEV10 = 00b Supply Current During Programming or Verify Input Low Voltage During Programming or VerifyDriving internal pull During Programming or Verify Down resistor AC Electrical Characteristics DC24M Power Up Recall Duration Gpio Operating Frequency 12.3 MHz Normal Strong Mode TRiseSStore Cycle Duration 12.5 Low Voltage Trigger Level Bwoa Crcprs SpimSpis Bwob Data Set up Time to Falling Edge of Sclk Data Out Delay from Falling Edge of Sclk 0V ≤ Vcc ≤Setup Time for a Repeated Start Condition Data Hold Time Data Setup Time 5V Operation Capacitive Load on Pins as Input Pin dependent. Temp = 25oC High Output Level VccCombined IOH budget Input Low Level 75 to Input Leakage Current Port 0 Analog Pins Gross tested to 1 μA Input Capacitance Port 0 Analog PinsLow power comparator LPC reference voltage range Vcc Average Input Offset Voltage Drift Psrrob PORLEV10 = 10b Vdd Value for Ppor Trip negative ramp PORLEV10 = 10b Ppor HysteresisVM20 = 011b VM20 = 100b Block Output Low Voltage During Programming orVerify Using factory trim values MHz Trimmed for 5V operationSee on Internal Main Oscillator Frequency for 6 MHz MHz Normal Strong Mode TRiseF Gpio Operating FrequencyVcc = 4.75V to TFallF Maximum Frequency 49.2 MHz 75V ≤ Vcc ≤ Maximum Input Clock Frequency 24.6 MHz 75V ≤ Vcc ≤ CRC Mode MHz due to 2 Over clockingSions Transmitter Maximum Input Clock Frequency 24.6 MHz Vcc ≥ 4.75V, 2 Stop Bits MHz due to 8 Over clocking 49.2 Data Out Delay from Falling Edge of Sclk 75V ≤ Vcc ≤ Switching Waveforms A b l e External Crystal Oscillator Startup Timing Diagram L e c t Part Numbering Nomenclature Ordering InformationCY8CNP102B-AXI CY8CNP102E-AXI Package Diagrams Thermal ImpedanceTqfp 81 oC/W GVCH/PYRS Document HistoryPyrs USB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions