L e c t | Cypress CY8CNP102E, CY8CNP102B guide

PRELIMINARY CY8CNP102B, CY8CNP102E

Switching Waveforms (continued)

Figure 11. External Crystal Oscillator Startup Timing Diagram

3 2 K

Se l e c t

F 3 2 K 2

3 2 k H z

T O S

Figure 12. 24 MHz Period Jitter (IMO) Timing Diagram

J it t e r 2 4 M 1

F 2 4 M

Figure 13. 32 kHz Period Jitter (ECO) Timing Diagram

J it t e r 3 2 k

F 3 2 K 2

Figure 14. Definition of Timing for Fast/Standard Mode on the I2C Bus

SDA
							~ ~		~ ~
t	f	t	LOWI2C	t	tSUDATI2C		tf	t	HDSTAI2C
	f		LOWI2C		r				HDSTAI2C
SCL
		tHDSTAI2C					~ ~		~ ~
		tHDSTAI2C			tHDDATI2C	tHIGHI2C	tSUSTAI2C	Sr
		S			tHDDATI2C	tHIGHI2C		Sr

tSPI2C tr tBUFI2C

tSUSTOI2C

P S

Document #: 001-43991 Rev. *D

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Cypress CY8CNP102E, CY8CNP102B manual External Crystal Oscillator Startup Timing Diagram, L e c t

Contents

Features Overview Logic Block Diagram Gpio PinoutsENW NVA2 NVWNVA1 ENA1 NvSRAM Data Memory PSoC NV Functional OverviewPSoC NV Core NvSRAM Operation Programmable Analog System Programmable Digital SystemAdditional System Resources PSoC Designer Software Subsystems Development ToolsEsigner Hardware Tools Designing with User ModulesUser Module and Source Code Development Flows Microhenry Picosecond Microsecond Cypress nvSRAM user ModuleParts per million Samples per second Absolute Maximum Ratings Operating Temperature3V Operation ESD DC Electrical Characteristics Cmrroa Psrroa Psrr OB Agnd = BandGap1 Agnd = 1.6 x BandGap1 DC Analog Reference SpecificationsCapacitor Unit Value Switch Cap Resistor Unit Value Continuous Time PORLEV10 = 00b Ppor Hysteresis Vdd Value for Ppor Trip positive rampPORLEV10 = 00b Vdd Value for Ppor Trip negative ramp PORLEV10 = 00b Driving internal pull Supply Current During Programming or VerifyInput Low Voltage During Programming or Verify During Programming or Verify Down resistor AC Electrical Characteristics DC24M Store Cycle Duration 12.5 Power Up Recall DurationGpio Operating Frequency 12.3 MHz Normal Strong Mode TRiseS Low Voltage Trigger Level Bwoa Spis CrcprsSpim Bwob Setup Time for a Repeated Start Condition Data Set up Time to Falling Edge of SclkData Out Delay from Falling Edge of Sclk 0V ≤ Vcc ≤ Data Hold Time Data Setup Time 5V Operation Combined IOH budget Capacitive Load on Pins as Input Pin dependent. Temp = 25oCHigh Output Level Vcc Input Low Level 75 to Low power comparator LPC reference voltage range Vcc Input Leakage Current Port 0 Analog PinsGross tested to 1 μA Input Capacitance Port 0 Analog Pins Average Input Offset Voltage Drift Psrrob VM20 = 011b PORLEV10 = 10b Vdd Value for Ppor Trip negative rampPORLEV10 = 10b Ppor Hysteresis VM20 = 100b Verify Output Low Voltage During Programming orBlock See on Using factory trim valuesMHz Trimmed for 5V operation Internal Main Oscillator Frequency for 6 MHz Vcc = 4.75V to MHz Normal Strong Mode TRiseFGpio Operating Frequency TFallF Maximum Frequency 49.2 MHz 75V ≤ Vcc ≤ Sions Transmitter Maximum Input Clock Frequency 24.6 MHz Maximum Input Clock Frequency 24.6 MHz 75V ≤ Vcc ≤ CRC ModeMHz due to 2 Over clocking Vcc ≥ 4.75V, 2 Stop Bits MHz due to 8 Over clocking 49.2 Data Out Delay from Falling Edge of Sclk 75V ≤ Vcc ≤ Switching Waveforms A b l e External Crystal Oscillator Startup Timing Diagram L e c t CY8CNP102B-AXI Part Numbering NomenclatureOrdering Information CY8CNP102E-AXI Tqfp Package DiagramsThermal Impedance 81 oC/W Pyrs Document HistoryGVCH/PYRS Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB