Switching Waveforms, A b l e | Cypress CY8CNP102B, CY8CNP102E

PRELIMINARY CY8CNP102B, CY8CNP102E

Switching Waveforms

Figure 8. AutoStore/Power Up RECALL

	STORE occurs only	No STORE occurs
VCC	if a SRAM write	without atleast one
VCC	has happened	SRAM write
	has happened	SRAM write

VSWITCH
tVCCRISE
AutoStore	tSTORE
tSTORE	tSTORE

POWER-UP RECALL

tHRECALL

Read & Write Inhibited

Figure 9. PLL Lock Timing Diagram

P L L

E n a b l e

T P L L S L E W

F P L L

	P L L	0
	G a in	0
	G a in

2 4 M H z

Figure 10. PLL Lock for Low Gain Setting Timing Diagram

P L L

E n a b l e

T P L L S L E W L O W			2 4 M H z

F P L L

	P L L
		1
	G a i n

Document #: 001-43991 Rev. *D

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Cypress CY8CNP102B, CY8CNP102E manual Switching Waveforms, A b l e

Contents

Overview Features Logic Block Diagram Pinouts GpioENW NVA1 NVWNVA2 ENA1 PSoC NV Core PSoC NV Functional OverviewNvSRAM Data Memory NvSRAM Operation Programmable Digital System Programmable Analog SystemAdditional System Resources Development Tools PSoC Designer Software SubsystemsEsigner Designing with User Modules Hardware ToolsUser Module and Source Code Development Flows Parts per million Cypress nvSRAM user ModuleMicrohenry Picosecond Microsecond Samples per second 3V Operation Operating TemperatureAbsolute Maximum Ratings ESD DC Electrical Characteristics Psrroa Cmrroa Psrr OB Capacitor Unit Value Switch Cap DC Analog Reference SpecificationsAgnd = BandGap1 Agnd = 1.6 x BandGap1 Resistor Unit Value Continuous Time PORLEV10 = 00b Vdd Value for Ppor Trip negative ramp Vdd Value for Ppor Trip positive rampPORLEV10 = 00b Ppor Hysteresis PORLEV10 = 00b Input Low Voltage During Programming or Verify Supply Current During Programming or VerifyDriving internal pull During Programming or Verify Down resistor DC24M AC Electrical Characteristics Gpio Operating Frequency 12.3 MHz Normal Strong Mode TRiseS Power Up Recall DurationStore Cycle Duration 12.5 Low Voltage Trigger Level Bwoa Spim CrcprsSpis Bwob Data Out Delay from Falling Edge of Sclk 0V ≤ Vcc ≤ Data Set up Time to Falling Edge of SclkSetup Time for a Repeated Start Condition Data Hold Time Data Setup Time 5V Operation High Output Level Vcc Capacitive Load on Pins as Input Pin dependent. Temp = 25oCCombined IOH budget Input Low Level 75 to Gross tested to 1 μA Input Capacitance Port 0 Analog Pins Input Leakage Current Port 0 Analog PinsLow power comparator LPC reference voltage range Vcc Average Input Offset Voltage Drift Psrrob PORLEV10 = 10b Ppor Hysteresis PORLEV10 = 10b Vdd Value for Ppor Trip negative rampVM20 = 011b VM20 = 100b Output Low Voltage During Programming or VerifyBlock MHz Trimmed for 5V operation Using factory trim valuesSee on Internal Main Oscillator Frequency for 6 MHz Gpio Operating Frequency MHz Normal Strong Mode TRiseFVcc = 4.75V to TFallF Maximum Frequency 49.2 MHz 75V ≤ Vcc ≤ MHz due to 2 Over clocking Maximum Input Clock Frequency 24.6 MHz 75V ≤ Vcc ≤ CRC ModeSions Transmitter Maximum Input Clock Frequency 24.6 MHz Vcc ≥ 4.75V, 2 Stop Bits MHz due to 8 Over clocking 49.2 Data Out Delay from Falling Edge of Sclk 75V ≤ Vcc ≤ A b l e Switching Waveforms L e c t External Crystal Oscillator Startup Timing Diagram Ordering Information Part Numbering NomenclatureCY8CNP102B-AXI CY8CNP102E-AXI Thermal Impedance Package DiagramsTqfp 81 oC/W Document History PyrsGVCH/PYRS Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB