Nvw, NVA1, NVA2, ENA1, ENA2, Eno, Xres, Vcap | Cypress CY8CNP102E

PRELIMINARY CY8CNP102B, CY8CNP102E

Table 1. Pin Definitions - 100-Pin TQFP (continued)

Pin Number	Pin Name			Type		Pin Definition
Pin Number	Pin Name		Digital		Analog	Pin Definition
			Digital		Analog
18	P5_7		IO			GPIO

19	P5_5		IO			GPIO

20	P5_3		IO			GPIO

21	P5_1		IO			GPIO

22	P1_7		IO			I2C Serial Clock (SCL), GPIO

23	P1_5		IO			I2C Serial Data (SDA), GPIO

24	P1_3		IO			GPIO

25	P1_1		IO			Serial Clock (SCL), Crystal (XTALin), GPIO

26	NV_W					Connect to pin 16 (NV_W to EN_W)

27 - 34	NC					Not connected on the die
35 - 39	Vss			Power		Ground

40 - 47	NC					Not connected on the die
48	DNU					Reserved for test modes - Do Not Use

49	NV_A1					Connect to pin 58 (NV_A1 to EN_A1)

50	NV_A2					Connect to pin 59 (NV_A2 to EN_A2)

51	P1_0		IO			Serial Data (SDA), Crystal (XTALout), GPIO

52	P1_2		IO			GPIO

53	P1_6		IO			GPIO

54	P5_0		IO			GPIO

55	P5_2		IO			GPIO

56	P5_4		IO			GPIO

57	P5_6		IO			GPIO

58	EN_A1					Connect to Pin 49 (EN_A1 to NV_A1)

59	EN_A2					Connect to Pin 50 (EN_A2 to NV_A2)

60	EN_O					Connect to Pin 76 (EN_O to NV_O)

61	EN_C					Connect to Pin 99 (EN_C to NV_C)

62	XRES			Input		Active high external reset (Internal Pull down)

63	VCAP			Power		External Capacitor connection for nvSRAM

64	Vcc			Power		Supply Voltage

65	P2_0		IO		I	Direct Switched Capacitor Block Input, GPIO

66	P2_2		IO		I	Direct Switched Capacitor Block Input, GPIO

67	P2_4		IO			External Analog GND, GPIO

68	P2_6		IO			External Voltage Ref, GPIO

69	P0_0		IO		I	Analog Column Mux Input, GPIO

70	P0_2		IO		IO	Analog Column Mux Input and Column Output

71	P0_4		IO		IO	Analog Column Mux Input and Column Output

72-73	NC					Not connected on the die
74	P0_6		IO		I	Analog Column Mux Input, GPIO

75	Vcc			Power		Supply Voltage

76	NV_O					Connect to Pin 60 (NV_O to EN_O)

77	DNU					Reserved for test modes - Do Not Use

78	NC					Not connected on the die
Document #: 001-43991 Rev. *D						Page 4 of 38

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Cypress CY8CNP102E, CY8CNP102B manual Nvw, NVA1, NVA2, ENA1, ENA2, Eno, Xres, Vcap, Nvo

Contents

Features Overview Logic Block Diagram Gpio PinoutsENW NVW NVA1NVA2 ENA1 PSoC NV Functional Overview PSoC NV CoreNvSRAM Data Memory NvSRAM Operation Programmable Analog System Programmable Digital SystemAdditional System Resources PSoC Designer Software Subsystems Development ToolsEsigner Hardware Tools Designing with User ModulesUser Module and Source Code Development Flows Cypress nvSRAM user Module Parts per millionMicrohenry Picosecond Microsecond Samples per second Operating Temperature 3V OperationAbsolute Maximum Ratings ESD DC Electrical Characteristics Cmrroa Psrroa Psrr OB DC Analog Reference Specifications Capacitor Unit Value Switch CapAgnd = BandGap1 Agnd = 1.6 x BandGap1 Resistor Unit Value Continuous Time Vdd Value for Ppor Trip positive ramp PORLEV10 = 00b Vdd Value for Ppor Trip negative rampPORLEV10 = 00b Ppor Hysteresis PORLEV10 = 00b Supply Current During Programming or Verify Input Low Voltage During Programming or VerifyDriving internal pull During Programming or Verify Down resistor AC Electrical Characteristics DC24M Power Up Recall Duration Gpio Operating Frequency 12.3 MHz Normal Strong Mode TRiseSStore Cycle Duration 12.5 Low Voltage Trigger Level Bwoa Crcprs SpimSpis Bwob Data Set up Time to Falling Edge of Sclk Data Out Delay from Falling Edge of Sclk 0V ≤ Vcc ≤Setup Time for a Repeated Start Condition Data Hold Time Data Setup Time 5V Operation Capacitive Load on Pins as Input Pin dependent. Temp = 25oC High Output Level VccCombined IOH budget Input Low Level 75 to Input Leakage Current Port 0 Analog Pins Gross tested to 1 μA Input Capacitance Port 0 Analog PinsLow power comparator LPC reference voltage range Vcc Average Input Offset Voltage Drift Psrrob PORLEV10 = 10b Vdd Value for Ppor Trip negative ramp PORLEV10 = 10b Ppor HysteresisVM20 = 011b VM20 = 100b Verify Output Low Voltage During Programming orBlock Using factory trim values MHz Trimmed for 5V operationSee on Internal Main Oscillator Frequency for 6 MHz MHz Normal Strong Mode TRiseF Gpio Operating FrequencyVcc = 4.75V to TFallF Maximum Frequency 49.2 MHz 75V ≤ Vcc ≤ Maximum Input Clock Frequency 24.6 MHz 75V ≤ Vcc ≤ CRC Mode MHz due to 2 Over clockingSions Transmitter Maximum Input Clock Frequency 24.6 MHz Vcc ≥ 4.75V, 2 Stop Bits MHz due to 8 Over clocking 49.2 Data Out Delay from Falling Edge of Sclk 75V ≤ Vcc ≤ Switching Waveforms A b l e External Crystal Oscillator Startup Timing Diagram L e c t Part Numbering Nomenclature Ordering InformationCY8CNP102B-AXI CY8CNP102E-AXI Package Diagrams Thermal ImpedanceTqfp 81 oC/W Pyrs Document HistoryGVCH/PYRS Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB