PRELIMINARY CY8CNP102B, CY8CNP102E
AC Operational Amplifier Specifications
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Table 17. 3.3V AC Operational Amplifier Specifications (CY8CNP102B)
Symbol | Description | Min | Typ | Max | Units | Notes |
TROA | Rising Settling Time to 0.1% of a 1V Step |
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| Power = High and |
| (10 pF load, Unity Gain) |
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| Opamp Bias = High is |
| Power = Low, Opamp Bias = Low | – | – | 3.92 | μs | not supported at |
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| Power = Medium, Opamp Bias = High | – | – | 0.72 | μs | |
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TSOA | Falling Settling Time to 0.1% of a 1V Step |
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| (10 pF load, Unity Gain) |
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| Power = Low, Opamp Bias = Low | – | – | 5.41 | μs |
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| Power = Medium, Opamp Bias = High | – | – | 0.72 | μs |
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SRROA | Rising Slew Rate (20% to 80%) of a 1V Step |
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| (10 pF load, Unity Gain) |
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| Power = Low, Opamp Bias = Low | 0.31 | – | – | V/μs |
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| Power = Medium, Opamp Bias = High | 2.7 | – | – | V/μs |
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SRFOA | Falling Slew Rate (20% to 80%) of a 1V Step |
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| (10 pF load, Unity Gain) |
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| Power = Low, Opamp Bias = Low | 0.24 | – | – | V/μs |
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| Power = Medium, Opamp Bias = High | 1.8 | – | – | V/μs |
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BWOA | Gain Bandwidth Product |
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| Power = Low, Opamp Bias = Low | 0.67 | – | – | MHz |
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| Power = Medium, Opamp Bias = High | 2.8 | – | – | MHz |
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ENOA | Noise at 1 kHz | – | 100 | – |
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| (Power = Medium, Opamp Bias = High) |
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AC Digital Block Specifications |
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Table 18. 3.3V AC Digital Block Specifications (CY8CNP102B) |
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Function | Description | Min | Typ | Max | Units | Notes |
All Functions | Maximum Block Clocking Frequency |
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| 24.6 | MHz | 3.0V ≤ Vcc ≤ 3.6V |
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Timer | Capture Pulse Width | 50[8] | – | – | ns |
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| Maximum Frequency, No Capture | – | – | 24.6 | MHz | 3.0V ≤ Vcc ≤ 3.6V. |
| Maximum Frequency, With Capture | – | – | 24.6 | MHz | 3.0V ≤ Vcc ≤ 3.6V. |
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Counter | Enable Pulse Width | 50[8] | – | – | ns |
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| Maximum Frequency, No Enable Input | – | – | 24.6 | MHz | 3.0V ≤ Vcc ≤3.6V. |
| Maximum Frequency, Enable Input | – | – | 24.6 | MHz | 3.0V ≤ Vcc ≤ 3.6V. |
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Dead Band | Kill Pulse Width: |
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| Asynchronous Restart Mode | 20 | – | – | ns |
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| Synchronous Restart Mode | 50[8] | – | – | ns |
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| Disable Mode | 50[8] | – | – | ns |
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| Maximum Frequency | – | – | 24.6 | MHz | 3.0V ≤ Vcc ≤ 3.6V |
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Note
8. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document #: | Page 19 of 38 |
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