Emerson MVME2500 manual Programming Model

Programming Model

Table 7-1 POR Configuration Settings (continued)

	CONFIG	CONFIG PINS	CONFIG	SELECTION	REMARKS
6	Boot Sequence	LGPL3/LFWP, LGPL5	11	CFG_BOOT_SEQ[1:0] =
				BOOT SEQUENCE
				DISABLED
7	Memory Debug	DMA2_DACK0	1	Debug information from
	Config			the DDR SDRAM
				controller is driven on the
				MSPCID and MDVAL signs
				(default)
8	DDR Debug	DMA2_DDONE0	1	Debug information is not
	Config			driven on ECC pins. ECC
				function in their normal
				mode (default).
9	ELBCECC Enable	MSRCID0	0	Default operation: eLBC
	Config			ECC checking is disabled
10	Platform Speed	LA23	1	CFG_PLAT_SPEED:1=CCB
				CLOCK > = 333 MHz
11	CORE 0 Speed	LA24	1	CFG_CORE0_SPEED:1=C	For 1200 MHz board
				ORE FREQ>= 1000 MHz	configuration
12			0	CFG_CORE0_SPEED:0=C	For 800 MHz board
				ORE FREQ<=1000 MHz	configuration
13	CORE 1 Speed	LA26	1	CFG_CORE1_SPEED:1=C	For 1200 MHz board
				ORE FREQ>=1000 MHz	configuration
14			0	CFG_CORE1_SPEED:0=C	For 800 MHz board
				ORE FREQ<=1000 MHz	configuration
15	DDR Controller	LA26	1	CFG_DDR_SPEED:1=DDR
	Speed			FREQ>= 500 MHz
16	Engineering use	LA[22:20]	111111	Default (for future use)
		UART_SOUT[0],	11
		TRIG_OUT,
		MSRCID[1],
		MSRCID[4],
		DMA1_DDONE_B[0]
17	SerDes Ref	TSEC_1588_ALARM	1	SerDes expects a 100
	Clock Config	_OUT1		MHz reference clock
				frequency (default).

114 MVME2500 Installation and Use (6806800L01H)