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Emerson MVME2500 manual Programmable Logic Device PLD Registers, PLD Revision Register, Pldrev

Models: MVME2500

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Memory Maps and Registers

5.5Programmable Logic Device (PLD) Registers

5.5.1PLD Revision Register

The MVME2500 provides a PLD revision register that can be read by the system software to determine the current version of the timers/registers PLD.

Table 5-4 PLD Revision Register

REG	PLD Revision Register - 0xFFDF0000

Bit	7	6	5	4	3	2	1	0

Field	PLD Rev

OPER	R

RESET	03

Field Description
PLD_REV	8-bit field containing the current timer/register PLD revision. The
	revision number starts at 01.

5.5.2PLD Year Register

The MVME2500 PLD provides an 8-bit register which contains the build year of the timers/registers PLD.

Table 5-5 PLD Year Register

REG	PLD Year Register - 0xFFDF0004

Bit	7	6	5	4	3	2	1	0

Field	PLD Rev

OPER	R

RESET	0A

84	MVME2500 Installation and Use (6806800L01H)

Page 84

Image 84

Emerson MVME2500 Programmable Logic Device PLD Registers, PLD Revision Register, PLD Year Register, Field Description

Contents

Installation and Use MVME2500P/N 6806800L01H January Embedded Computing for Business-Critical ContinuityTMTrademarks Limited and Restricted Rights LegendContact Address Contents 2 Hardware Preparation and Installation3 Controls, LEDs, and Connectors Contents Contents Contents Contents Contents 6 Boot System5 Memory Maps and Registers Contents B.1 Emerson Network Power - Embedded Computing DocumentsA Replacing the Battery 7 Programming ModelContents Contents Safety Notes Sicherheitshinweise IndexMVME2500 Installation and Use 6806800L01H ListofTables List of Tables MVME2500 Installation and Use 6806800L01HList of Figures Figure A-1List of Figures MVME2500 Installation and Use 6806800L01HOverview of Contents About this ManualAbbreviations About this Manual About this Manual Conventions About this ManualCourier + Bold ReferenceMVME2500 Installation and Use 6806800L01H About this Manual About this ManualNotation Description Logical ORSummary of Changes About this ManualThis manual has been revised and replaces all prior editions  Edited Figure Component Layout Updated Appendix B, Related  Updated Figure Component Layout onAbout this Manual About this Manual pageTable 1-1 Key Features of the MVME2500 IntroductionChapter 1.1 OverviewTable 1-1 Key Features of the MVME2500 continued Introduction1.2 Standard Compliances Table 1-2 Board Standard CompliancesTable 1-1 Key Features of the MVME2500 continued Introduction1.3 Mechanical Data 1.4 Ordering InformationTable 1-3 Mechanical Data Table 1-4 Available Board VariantsTable 1-5 Available Board Accessories Introduction1.5 Product Identification Figure 1-1 Serial Number LocationMVME2500 Installation and Use 6806800L01H IntroductionHardware Preparation and Installation 2.1 OverviewChapter Hardware Preparation and Installation 2.2 Unpacking and Inspecting the Board2.3 Requirements Shipment Inspection2.3.1 Environmental Requirements Table 2-1 Environmental RequirementsHardware Preparation and Installation 2.3.2 Power Requirements Table 2-2 Power RequirementsHardware Preparation and Installation 2.4 Configuring the Board 2.3.3 Equipment RequirementsHardware Preparation and Installation 2.5 Installing Accessories 2.5.1 Rear Transition ModuleHardware Preparation and Installation Installation Procedure 2.5.2 PMC/XMC SupportHardware Preparation and Installation 2.6 Installing and Removing the Board Hardware Preparation and InstallationHardware Preparation and Installation 2.7 Completing the Installation Hardware Preparation and InstallationControls, LEDs,and Connectors 3.1 Board LayoutFigure 3-1 Component Layout ChapterControls, LEDs, and Connectors Figure 3-2 Front Panel LEDs, Connectors and Switches3.2 Front Panel MVME2500 Installation and Use 6806800L01H3.2.1 Reset Switch 3.3 LEDs3.3.1 Front Panel LEDs Figure 3-3 Front Panel LEDsTable 3-1 Front Panel LEDs Controls, LEDs, and Connectors3.4 Connectors 3.3.2 Onboard LEDsTable 3-2 Onboard LEDs Status Controls, LEDs, and Connectors3.4.1 Front Panel Connectors Table 3-3 Front Panel Tri-Speed Ethernet Connector J13.4.1.1 RJ45 with Integrated Magnetics J1 Controls, LEDs, and ConnectorsTable 3-3 Front Panel Tri-Speed Ethernet Connector J1 continued 3.4.1.2 Front Panel Serial Port J4Table 3-4 Front Panel Serial Port J4 Controls, LEDs, and Connectors3.4.1.3 USB Connector J5 3.4.1.4 VMEBus P1 ConnectorTable 3-5 USB Connector J5 Table 3-6 VMEbus P1 ConnectorTable 3-6 VMEbus P1 Connector continued Controls, LEDs, and ConnectorsIRQ4 3.4.1.5 VMEBus P2 Connector Table 3-7 VMEbus P2 ConnectorControls, LEDs, and Connectors 3.4.2 Onboard Connectors 3.4.2.1 Flash Program Connector P7Table 3-7 VMEbus P2 Connector continued Table 3-8 Flash Programming Header P73.4.2.2 SATA Connector J3 Table 3-9 Custom SATA Connector J3Table 3-8 Flash Programming Header P7 continued Controls, LEDs, and Connectors3.4.2.3 PMC Connectors Table 3-9 Custom SATA Connector J3 continuedTable 3-10 PMC J11 Connector Controls, LEDs, and ConnectorsTable 3-10 PMC J11 Connector continued Table 3-11 PMC J12 ConnectorControls, LEDs, and Connectors Table 3-11 PMC J12 Connector continued Table 3-12 PMC J13 ConnectorControls, LEDs, and Connectors Table 3-12 PMC J13 Connector continued Controls, LEDs, and ConnectorsTable 3-13 PMC J14 Connector Controls, LEDs, and ConnectorsTable 3-12 PMC J13 Connector continued 3.4.2.4 JTAG Connector P6 Table 3-13 PMC J14 Connector continuedTable 3-14 JTAG Connector P6 Controls, LEDs, and ConnectorsTable 3-14 JTAG Connector P6 continued Controls, LEDs, and Connectors3.4.2.5 COP Connector P6 3.4.2.6 SD Connector J2Table 3-16 SD Connector J2 Table 3-15 COP Header P103.4.2.7 XMC Connector XJ2 Table 3-16 SD Connector J2 continuedTable 3-17 XMC Connector XJ2 Pinout Controls, LEDs, and Connectors3.4.2.8 Miscellaneous P2020 Debug Connectors Table 3-17 XMC Connector XJ2 Pinout continuedTable 3-18 P20x0 Debug Header Controls, LEDs, and Connectors3.5 Switches 3.5.1 Geographical Address Switch S1Table 3-18 P20x0 Debug Header continued Controls, LEDs, and ConnectorsFigure 3-5 Geographical Address Switch Table 3-19 Geographical Address SwitchControls, LEDs, and Connectors 3.5.2 SMT Configuration Switch S2 Figure 3-6 SMT Configuration Switch PositionTable 3-20 Geographical Address Switch Settings Controls, LEDs, and ConnectorsTable 3-20 Geographical Address Switch Settings continued Controls, LEDs, and Connectors4.1 Block Diagram Figure 4-1 Block DiagramFunctional Description 4.2 Chipset4.2.1 e500 Processor Core 4.2.2 Integrated Memory ControllerFunctional Description 4.2.3 PCI Express Interface 4.2.4 Local Bus Controller LBC4.2.5 Secure Digital Hub Controller SDHC 4.2.6 I2C Interface4.2.8 DUART 4.2.9 DMA Controller4.2.10 Enhanced Three-Speed Ethernet Controller eTSEC 4.2.11 General Purpose I/O GPIO4.4 Timers 4.2.14 P20x0 Hardware Configuration Pins4.3 System Memory 4.2.13 Common On-Chip Processor COP4.4.2 Internal Timer 4.4.3 Watchdog Timer4.4.4 FPGA Tick Timer 4.5 Ethernet Interfaces4.6 SPI Bus Interface 4.6.1 SPI Flash Memory4.6.2 SPI Flash Programming Functional Description4.6.3 Firmware Redundancy Functional DescriptionFigure 4-2 SPI Device Multiplexing Logic Functional Description4.6.4 Crisis Recovery 4.7 Front UART ControlFunctional Description 4.8 Rear UART Control 4.9 PMC/XMC SitesFunctional Description 4.10 SATA Interface 4.9.1 PMC Add-on Card4.9.2 XMC Add-on Card Functional Description4.11 VME Support 4.12 USB4.13 I2C Devices 4.11.1 Tsi148 VME Controller4.14 Reset/Control FPGA 4.15 Power Management4.15.1 Onboard Voltage Supply Requirement Table 4-1 Voltage Supply Requirement4.15.2 Power Up Sequencing Requirements Functional DescriptionTable 4-1 Voltage Supply Requirement 4.17 Reset Structure Figure 4-3 Clock Distribution Diagram4.16 Clock Structure Functional Description4.19 Real-Time Clock Battery 4.17.1 Reset Sequence4.18 Thermal Management Table 4-2 Thermal Interrupt Threshold4.20.1 POST Code Indicator Table 4-3 POST Code Indicator on the LED4.20 Debugging Support 4.20.2 JTAG Chain and BoardTable 4-4 Transition Module Features 4.21 Rear Transition Module RTM4.20.3 Custom Debugging Functional DescriptionMVME2500 Installation and Use 6806800L01H Functional DescriptionMemory Maps and Registers 5.1 Overview5.2 Memory Map Table 5-1 Physical Address Map5.3 Flash Memory Map 5.4 Linux Devices Memory MapMemory Maps and Registers Table 5-2 Flash Memory MapTable 5-3 Linux Devices Memory Map Memory Maps and Registers8-bit field containing the current timer/register PLD revision. The 5.5 Programmable Logic Device PLD Registers5.5.1 PLD Revision Register 5.5.2 PLD Year Register5.5.3 PLD Month Register 5.5.4 PLD Day Register5.5.5 PLD Sequence Register Table 5-6 PLD Month Register5.5.6 PLD Power Good Monitor Register Table 5-9 PLD Power Good Monitor Register1.2V Supply power good indicator 1.8V Supply power good indicator5.5.7 PLD LED Control Register Table 5-10 PLD LED Control RegisterLEDs Status on page Memory Maps and Registers5.5.8 PLD PCI/PMC/XMC Monitor Register Table 5-11 PLD PCI/PMC/XMC Monitor RegisterMemory Maps and Registers Field Description5.5.9 PLD U-Boot and TSI Monitor Register 5.5.10 PLD Boot Bank RegisterTable 5-12 PLD U-Boot and TSI Monitor Register Table 5-13 PLD Boot Bank RegisterTable 5-13 PLD Boot Bank Register BOOTBLOCKABoot Block Manual Selector Switch Actual Boot Bank5.5.11 PLD Write Protect and I2C Debug Register Table 5-14 PLD Write Protect and I2C Debug RegisterMemory Maps and Registers Field DescriptionMemory Maps and Registers 5.5.12 PLD Test Register 5.5.13 PLD Test RegisterTable 5-15 PLD Test Register Table 5-16 PLD Test Register5.5.14 PLD GPIO2 Interrupt Register Table 5-17 PLD GPIO2 Interrupt RegisterMemory Maps and Registers Field Description5.5.15 PLD Shutdown and Reset Control and Reset Reason Register Table 5-18 PLD Shutdown and Reset Control and Reset Reason RegisterAUTOSHDNMASK Automatic Shutdown Mask5.5.16 PLD Watchdog Timer Refresh Register Table 5-19 PLD Watchdog Timer Refresh RegisterMemory Maps and Registers Field Description5.5.18 PLD Watchdog Timer Count Register Table 5-21 PLD Watchdog Timer Count Register5.5.17 PLD Watchdog Control Register Table 5-20 PLD Watchdog Control Register5.6 External Timer Registers 5.6.1 Prescaler RegisterTable 5-22 Prescaler Register Memory Maps and Registers5.6.2 Control Registers Table 5-23 Control RegistersMemory Maps and Registers 5.6.3 Compare High and Low Word Registers Table 5-24 Compare High Word RegistersTable 5-25 Compare Low Word Registers Memory Maps and Registers5.6.4 Counter High and Low Word Registers Table 5-26 Counter High Word RegistersTable 5-27 Counter Low Word Registers Memory Maps and RegistersMVME2500 Installation and Use 6806800L01H Memory Maps and RegistersBoot System 6.2 Accessing U-Boot6.1 Overview Chapter6.3 Boot Options 6.3.1 Booting from a NetworkBoot System setenv netmask netmask6.3.2 Booting from an Optional SATA Drive 6.3.3 Booting from a USB Drive# option usb - interface, 01 - device 0 partition Boot System6.3.4 Booting from an SD Card 6.3.5 Booting VxWorks Through the Network# option mmc - interface, 01 - device 0 partition Boot System6.4 Using the Persistent Memory Feature Boot SystemAnalyzing Kernel Log Files after a Kernel Panic 6.5 MVME2500 Specific U-Boot Commands Table 6-1 MVME2500 Specific U-Boot CommandsBoot System Table 6-1 MVME2500 Specific U-Boot Commands continued Boot System6.6 Updating U-Boot Boot SystemTable 6-1 MVME2500 Specific U-Boot Commands continued Boot System 4. Erase 0x90000 bytes starting at SPI address 0 sf erase 0Boot System MVME2500 Installation and Use 6806800L01H7.2 Reset Configuration Table 7-1 POR Configuration SettingsProgramming Model 7.1 OverviewTable 7-1 POR Configuration Settings continued Programming ModelTable 7-1 POR Configuration Settings continued mode either RTBI, RGMIoperates using the RGMII Programming ModelTable 7-1 POR Configuration Settings continued Programming Model7.3 Interrupt Controller Table 7-2 MVME2500 Interrupt ListProgramming Model 7.4 I2C Bus Device Addressing 7.5 Ethernet PHY AddressTable 7-3 I2C Bus Device Addressing Table 7-4 PHY Types and MII Management Bus Address7.6 Other Software Considerations 7.6.1 MRAM7.6.2 Real Time Clock 7.6.3 Quad UART7.6.4 LBC Timing Parameters Table 7-5 LBC Timing ParametersProgramming Model Field Description7.7 Clock Distribution Table 7-6 Clock DistributionProgramming Model 7.7.1 System Clock Table 7-6 Clock Distribution continuedTable 7-7 System Clock Programming Model7.7.2 Real Time Clock Input 7.7.3 Local Bus Controller Clock DivisorProgramming Model MVME2500 Installation and Use 6806800L01H Programming ModelReplacing the Battery A.1 Replacing the BatteryFigure A-1 Battery Location Appendix AReplacing the Battery Replacing the Battery Replacement ProcedureTo replace the battery, proceed as follows 1. Remove the old battery 2. Install the new battery with the plus sign + facing upReplacing the Battery MVME2500 Installation and Use 6806800L01HB.1 Emerson Network Power - Embedded Computing Documents Table B-1 Emerson Network Power - Embedded Computing PublicationsRelated Documentation Appendix BB.3 Related Specifications Table B-3 Related SpecificationsB.2 Manufacturers’ Documents Related DocumentationTable B-3 Related Specifications PCI-X Protocol Addendum to the PCI Local Bus Specification PCI-X PTRelated Documentation IEEE Standard for a Common Mezzanine Card CMC Family IEEE StdMVME2500 Installation and Use 6806800L01H Related DocumentationSafety Notes EMC Results pending testingInstallation Safety NotesOperation Cabling and Connectors Safety NotesBattery Safety NotesSicherheitshinweise Betrieb SicherheitshinweiseInstallation SicherheitshinweiseBeschädigung von Schaltkreisen Kabel und Stecker BatterieSicherheitshinweise Bei Fragen wenden Sie sich an Ihren SystemverwalterUmweltschutz SicherheitshinweiseMVME2500 Installation and Use 6806800L01H SicherheitshinweiseIndex Index MVME2500 Installation and Use 6806800L01HPage HOW TO REACH LITERATURE AND TECHNICAL SUPPORT

5.5Programmable Logic Device (PLD) Registers

5.5.1PLD Revision Register

Table 5-4 PLD Revision Register

Field Description

PLD_REV

8-bit field containing the current timer/register PLD revision. The

revision number starts at 01.

5.5.2PLD Year Register

Table 5-5 PLD Year Register