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Emerson MVME2500 manual 17 PLD GPIO2 Interrupt Register, Memory Maps and Registers

Models: MVME2500

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Memory Maps and Registers

5.5.14 PLD GPIO2 Interrupt Register

The Abort switch, Tick Timer 0, 1 and 2 interrupts are ORed together. The MVME2500 provides an interrupt register that the system software reads to determine which device the interrupt originated from. GPIO2 will be driven "low" if any of the interrupts asserts.

Table 5-17 PLD GPIO2 Interrupt Register

REG	PLD Write Protect I2C Debug- 0xFFDF0095

Bit	7	6		5		4	3	2	1	0

Field	RSVD	RSVD		RSVD		RSVD	NMI	TICK0_INT	TICK1_INT	TICK2_INT

OPER	R

RESET	0	0		0		0	0	0	0	0

	Field Description
	NMI		Abort switch interrupt if pressed less than three seconds.
			1		- Interrupt enabled
			0		- No Interrupt
	TICK0_INT		Tick Timer 0 interrupt
			1		- Interrupt enabled
			0		- No Interrupt
	TICK1_INT		Tick Timer 1 interrupt
			1		- Interrupt enabled
			0		- No Interrupt
	TICK2_INT		Tick Timer 2 interrupt
			1		- Interrupt enabled
			0		- No Interrupt

94	MVME2500 Installation and Use (6806800L01H)

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Emerson MVME2500 manual 17 PLD GPIO2 Interrupt Register, Memory Maps and Registers, Field Description

Contents

P/N 6806800L01H January Installation and UseMVME2500 Embedded Computing for Business-Critical ContinuityTMLimited and Restricted Rights Legend TrademarksContact Address 2 Hardware Preparation and Installation Contents3 Controls, LEDs, and Connectors Contents Contents Contents 6 Boot System Contents Contents5 Memory Maps and Registers A Replacing the Battery ContentsB.1 Emerson Network Power - Embedded Computing Documents 7 Programming ModelSafety Notes Sicherheitshinweise Index Contents ContentsMVME2500 Installation and Use 6806800L01H ListofTables List of Tables MVME2500 Installation and Use 6806800L01HList of Figures Figure A-1List of Figures MVME2500 Installation and Use 6806800L01HAbout this Manual Overview of ContentsAbbreviations About this Manual About this Manual Courier + Bold ConventionsAbout this Manual ReferenceNotation MVME2500 Installation and Use 6806800L01HAbout this Manual About this Manual Description Logical ORThis manual has been revised and replaces all prior editions Summary of ChangesAbout this Manual  Edited Figure Component LayoutAbout this Manual About this Manual  Updated Appendix B, Related Updated Figure Component Layout on pageChapter Table 1-1 Key Features of the MVME2500Introduction 1.1 OverviewTable 1-1 Key Features of the MVME2500 continued IntroductionTable 1-1 Key Features of the MVME2500 continued 1.2 Standard CompliancesTable 1-2 Board Standard Compliances IntroductionTable 1-3 Mechanical Data 1.3 Mechanical Data1.4 Ordering Information Table 1-4 Available Board VariantsTable 1-5 Available Board Accessories IntroductionMVME2500 Installation and Use 6806800L01H 1.5 Product IdentificationFigure 1-1 Serial Number Location Introduction2.1 Overview Hardware Preparation and InstallationChapter 2.3 Requirements Hardware Preparation and Installation2.2 Unpacking and Inspecting the Board Shipment InspectionTable 2-1 Environmental Requirements 2.3.1 Environmental RequirementsHardware Preparation and Installation Table 2-2 Power Requirements 2.3.2 Power RequirementsHardware Preparation and Installation 2.3.3 Equipment Requirements 2.4 Configuring the BoardHardware Preparation and Installation 2.5.1 Rear Transition Module 2.5 Installing AccessoriesHardware Preparation and Installation 2.5.2 PMC/XMC Support Installation ProcedureHardware Preparation and Installation 2.6 Installing and Removing the Board Hardware Preparation and InstallationHardware Preparation and Installation 2.7 Completing the Installation Hardware Preparation and InstallationFigure 3-1 Component Layout Controls, LEDs,and Connectors3.1 Board Layout Chapter3.2 Front Panel Controls, LEDs, and ConnectorsFigure 3-2 Front Panel LEDs, Connectors and Switches MVME2500 Installation and Use 6806800L01H3.3.1 Front Panel LEDs 3.2.1 Reset Switch3.3 LEDs Figure 3-3 Front Panel LEDsTable 3-1 Front Panel LEDs Controls, LEDs, and ConnectorsTable 3-2 Onboard LEDs Status 3.4 Connectors3.3.2 Onboard LEDs Controls, LEDs, and Connectors3.4.1.1 RJ45 with Integrated Magnetics J1 3.4.1 Front Panel ConnectorsTable 3-3 Front Panel Tri-Speed Ethernet Connector J1 Controls, LEDs, and ConnectorsTable 3-4 Front Panel Serial Port J4 Table 3-3 Front Panel Tri-Speed Ethernet Connector J1 continued3.4.1.2 Front Panel Serial Port J4 Controls, LEDs, and ConnectorsTable 3-5 USB Connector J5 3.4.1.3 USB Connector J53.4.1.4 VMEBus P1 Connector Table 3-6 VMEbus P1 ConnectorControls, LEDs, and Connectors Table 3-6 VMEbus P1 Connector continuedIRQ4 Table 3-7 VMEbus P2 Connector 3.4.1.5 VMEBus P2 ConnectorControls, LEDs, and Connectors Table 3-7 VMEbus P2 Connector continued 3.4.2 Onboard Connectors3.4.2.1 Flash Program Connector P7 Table 3-8 Flash Programming Header P7Table 3-8 Flash Programming Header P7 continued 3.4.2.2 SATA Connector J3Table 3-9 Custom SATA Connector J3 Controls, LEDs, and ConnectorsTable 3-10 PMC J11 Connector 3.4.2.3 PMC ConnectorsTable 3-9 Custom SATA Connector J3 continued Controls, LEDs, and ConnectorsTable 3-11 PMC J12 Connector Table 3-10 PMC J11 Connector continuedControls, LEDs, and Connectors Table 3-12 PMC J13 Connector Table 3-11 PMC J12 Connector continuedControls, LEDs, and Connectors Table 3-12 PMC J13 Connector continued Controls, LEDs, and ConnectorsControls, LEDs, and Connectors Table 3-13 PMC J14 ConnectorTable 3-12 PMC J13 Connector continued Table 3-14 JTAG Connector P6 3.4.2.4 JTAG Connector P6Table 3-13 PMC J14 Connector continued Controls, LEDs, and ConnectorsTable 3-14 JTAG Connector P6 continued Controls, LEDs, and ConnectorsTable 3-16 SD Connector J2 3.4.2.5 COP Connector P63.4.2.6 SD Connector J2 Table 3-15 COP Header P10Table 3-17 XMC Connector XJ2 Pinout 3.4.2.7 XMC Connector XJ2Table 3-16 SD Connector J2 continued Controls, LEDs, and ConnectorsTable 3-18 P20x0 Debug Header 3.4.2.8 Miscellaneous P2020 Debug ConnectorsTable 3-17 XMC Connector XJ2 Pinout continued Controls, LEDs, and ConnectorsTable 3-18 P20x0 Debug Header continued 3.5 Switches3.5.1 Geographical Address Switch S1 Controls, LEDs, and ConnectorsTable 3-19 Geographical Address Switch Figure 3-5 Geographical Address SwitchControls, LEDs, and Connectors Table 3-20 Geographical Address Switch Settings 3.5.2 SMT Configuration Switch S2Figure 3-6 SMT Configuration Switch Position Controls, LEDs, and ConnectorsTable 3-20 Geographical Address Switch Settings continued Controls, LEDs, and ConnectorsFunctional Description 4.1 Block DiagramFigure 4-1 Block Diagram 4.2 Chipset4.2.2 Integrated Memory Controller 4.2.1 e500 Processor CoreFunctional Description 4.2.5 Secure Digital Hub Controller SDHC 4.2.3 PCI Express Interface4.2.4 Local Bus Controller LBC 4.2.6 I2C Interface4.2.10 Enhanced Three-Speed Ethernet Controller eTSEC 4.2.8 DUART4.2.9 DMA Controller 4.2.11 General Purpose I/O GPIO4.3 System Memory 4.4 Timers4.2.14 P20x0 Hardware Configuration Pins 4.2.13 Common On-Chip Processor COP4.4.4 FPGA Tick Timer 4.4.2 Internal Timer4.4.3 Watchdog Timer 4.5 Ethernet Interfaces4.6.2 SPI Flash Programming 4.6 SPI Bus Interface4.6.1 SPI Flash Memory Functional Description4.6.3 Firmware Redundancy Functional DescriptionFigure 4-2 SPI Device Multiplexing Logic Functional Description4.7 Front UART Control 4.6.4 Crisis RecoveryFunctional Description 4.9 PMC/XMC Sites 4.8 Rear UART ControlFunctional Description 4.9.2 XMC Add-on Card 4.10 SATA Interface4.9.1 PMC Add-on Card Functional Description4.13 I2C Devices 4.11 VME Support4.12 USB 4.11.1 Tsi148 VME Controller4.15.1 Onboard Voltage Supply Requirement 4.14 Reset/Control FPGA4.15 Power Management Table 4-1 Voltage Supply RequirementFunctional Description 4.15.2 Power Up Sequencing RequirementsTable 4-1 Voltage Supply Requirement 4.16 Clock Structure 4.17 Reset StructureFigure 4-3 Clock Distribution Diagram Functional Description4.18 Thermal Management 4.19 Real-Time Clock Battery4.17.1 Reset Sequence Table 4-2 Thermal Interrupt Threshold4.20 Debugging Support 4.20.1 POST Code IndicatorTable 4-3 POST Code Indicator on the LED 4.20.2 JTAG Chain and Board4.20.3 Custom Debugging Table 4-4 Transition Module Features4.21 Rear Transition Module RTM Functional DescriptionMVME2500 Installation and Use 6806800L01H Functional Description5.2 Memory Map Memory Maps and Registers5.1 Overview Table 5-1 Physical Address MapMemory Maps and Registers 5.3 Flash Memory Map5.4 Linux Devices Memory Map Table 5-2 Flash Memory MapTable 5-3 Linux Devices Memory Map Memory Maps and Registers5.5.1 PLD Revision Register 8-bit field containing the current timer/register PLD revision. The5.5 Programmable Logic Device PLD Registers 5.5.2 PLD Year Register5.5.5 PLD Sequence Register 5.5.3 PLD Month Register5.5.4 PLD Day Register Table 5-6 PLD Month Register1.2V Supply power good indicator 5.5.6 PLD Power Good Monitor RegisterTable 5-9 PLD Power Good Monitor Register 1.8V Supply power good indicatorLEDs Status on page 5.5.7 PLD LED Control RegisterTable 5-10 PLD LED Control Register Memory Maps and RegistersMemory Maps and Registers 5.5.8 PLD PCI/PMC/XMC Monitor RegisterTable 5-11 PLD PCI/PMC/XMC Monitor Register Field DescriptionTable 5-12 PLD U-Boot and TSI Monitor Register 5.5.9 PLD U-Boot and TSI Monitor Register5.5.10 PLD Boot Bank Register Table 5-13 PLD Boot Bank RegisterBoot Block Manual Selector Switch Table 5-13 PLD Boot Bank RegisterBOOTBLOCKA Actual Boot BankMemory Maps and Registers 5.5.11 PLD Write Protect and I2C Debug RegisterTable 5-14 PLD Write Protect and I2C Debug Register Field DescriptionMemory Maps and Registers Table 5-15 PLD Test Register 5.5.12 PLD Test Register5.5.13 PLD Test Register Table 5-16 PLD Test RegisterMemory Maps and Registers 5.5.14 PLD GPIO2 Interrupt RegisterTable 5-17 PLD GPIO2 Interrupt Register Field DescriptionAUTOSHDNMASK 5.5.15 PLD Shutdown and Reset Control and Reset Reason RegisterTable 5-18 PLD Shutdown and Reset Control and Reset Reason Register Automatic Shutdown MaskMemory Maps and Registers 5.5.16 PLD Watchdog Timer Refresh RegisterTable 5-19 PLD Watchdog Timer Refresh Register Field Description5.5.17 PLD Watchdog Control Register 5.5.18 PLD Watchdog Timer Count RegisterTable 5-21 PLD Watchdog Timer Count Register Table 5-20 PLD Watchdog Control RegisterTable 5-22 Prescaler Register 5.6 External Timer Registers5.6.1 Prescaler Register Memory Maps and RegistersTable 5-23 Control Registers 5.6.2 Control RegistersMemory Maps and Registers Table 5-25 Compare Low Word Registers 5.6.3 Compare High and Low Word RegistersTable 5-24 Compare High Word Registers Memory Maps and RegistersTable 5-27 Counter Low Word Registers 5.6.4 Counter High and Low Word RegistersTable 5-26 Counter High Word Registers Memory Maps and RegistersMVME2500 Installation and Use 6806800L01H Memory Maps and Registers6.1 Overview Boot System6.2 Accessing U-Boot ChapterBoot System 6.3 Boot Options6.3.1 Booting from a Network setenv netmask netmask# option usb - interface, 01 - device 0 partition 6.3.2 Booting from an Optional SATA Drive6.3.3 Booting from a USB Drive Boot System# option mmc - interface, 01 - device 0 partition 6.3.4 Booting from an SD Card6.3.5 Booting VxWorks Through the Network Boot SystemBoot System 6.4 Using the Persistent Memory FeatureAnalyzing Kernel Log Files after a Kernel Panic Table 6-1 MVME2500 Specific U-Boot Commands 6.5 MVME2500 Specific U-Boot CommandsBoot System Table 6-1 MVME2500 Specific U-Boot Commands continued Boot SystemBoot System 6.6 Updating U-BootTable 6-1 MVME2500 Specific U-Boot Commands continued Boot System 4. Erase 0x90000 bytes starting at SPI address 0 sf erase 0Boot System MVME2500 Installation and Use 6806800L01HProgramming Model 7.2 Reset ConfigurationTable 7-1 POR Configuration Settings 7.1 OverviewTable 7-1 POR Configuration Settings continued Programming Modeloperates using the RGMII Table 7-1 POR Configuration Settings continuedmode either RTBI, RGMI Programming ModelTable 7-1 POR Configuration Settings continued Programming ModelTable 7-2 MVME2500 Interrupt List 7.3 Interrupt ControllerProgramming Model Table 7-3 I2C Bus Device Addressing 7.4 I2C Bus Device Addressing7.5 Ethernet PHY Address Table 7-4 PHY Types and MII Management Bus Address7.6.2 Real Time Clock 7.6 Other Software Considerations7.6.1 MRAM 7.6.3 Quad UARTProgramming Model 7.6.4 LBC Timing ParametersTable 7-5 LBC Timing Parameters Field DescriptionTable 7-6 Clock Distribution 7.7 Clock DistributionProgramming Model Table 7-7 System Clock 7.7.1 System ClockTable 7-6 Clock Distribution continued Programming Model7.7.3 Local Bus Controller Clock Divisor 7.7.2 Real Time Clock InputProgramming Model MVME2500 Installation and Use 6806800L01H Programming ModelFigure A-1 Battery Location Replacing the BatteryA.1 Replacing the Battery Appendix AReplacing the Battery To replace the battery, proceed as follows 1. Remove the old battery Replacing the BatteryReplacement Procedure 2. Install the new battery with the plus sign + facing upReplacing the Battery MVME2500 Installation and Use 6806800L01HRelated Documentation B.1 Emerson Network Power - Embedded Computing DocumentsTable B-1 Emerson Network Power - Embedded Computing Publications Appendix BB.2 Manufacturers’ Documents B.3 Related SpecificationsTable B-3 Related Specifications Related DocumentationRelated Documentation Table B-3 Related SpecificationsPCI-X Protocol Addendum to the PCI Local Bus Specification PCI-X PT IEEE Standard for a Common Mezzanine Card CMC Family IEEE StdMVME2500 Installation and Use 6806800L01H Related DocumentationSafety Notes EMC Results pending testingSafety Notes InstallationOperation Cabling and Connectors Safety NotesBattery Safety NotesSicherheitshinweise Betrieb SicherheitshinweiseSicherheitshinweise InstallationBeschädigung von Schaltkreisen Sicherheitshinweise Kabel und SteckerBatterie Bei Fragen wenden Sie sich an Ihren SystemverwalterUmweltschutz SicherheitshinweiseMVME2500 Installation and Use 6806800L01H SicherheitshinweiseIndex Index MVME2500 Installation and Use 6806800L01HPage HOW TO REACH LITERATURE AND TECHNICAL SUPPORT