PLD U-Boot and TSI Monitor Register | Emerson MVME2500 guide

Memory Maps and Registers

5.5.9PLD U-Boot and TSI Monitor Register

The MVME2500 PLD provides an 8-bit register which indicates the status of the U-Boot's normal environment switch and TSI interface signals.

Table 5-12 PLD U-Boot and TSI Monitor Register

REG	PLD PCI_PMC_XMC_MNTR - 0xFFDF001F

Bit	7	6	5		4		3	2	1	0

Field	RSVD	RSVD	RSVD		RSVD		RSVD	BDFAIL_N	NORMAL_ENV	SCON

OPER	R

RESET	0	0	0		0		0	X	X	X

	Field Description
	BDFAIL_N		TSI148 BDFAIL_N Pin out
			1	- No TSI Fail
			0	- TSI Fail
	NORMAL_ENV		Normal Environment Switch Indicator
			1	- Use safe ENV
			0	- Use normal ENV
	SCON		System Controller Indicator

1 - System Controller

0- Non-system Controller

5.5.10PLD Boot Bank Register

The MVME2500 PLD provides an 8-bit register which is used to declare successful U-Boot loading, indicating the SPI boot bank priority and actual SPI bank it booted from.

Table 5-13 PLD Boot Bank Register

REG	PLD Boot Bank - 0xFFDF0050

Bit	7	6	5	4	3	2	1	0

MVME2500 Installation and Use (6806800L01H)

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Emerson MVME2500 manual PLD U-Boot and TSI Monitor Register, PLD Boot Bank Register

Contents

MVME2500 Contact Address Contents Contents Contents Memory Maps and Registers Emerson Network Power Embedded Computing Documents Safety Notes Sicherheitshinweise Index List of Tables List of Tables Figure A-1 List of Figures List of Figures Abbreviations Overview of ContentsAbout this Manual About this Manual USB ConventionsVita VME About this Manual About this Manual Summary of Changes Documentation, on Overview Key Features of the MVME2500Introduction  8 KB VPD Eeprom IntroductionKB Mram Board Standard Compliances Standard Compliances Ordering Information Mechanical DataMechanical Data Available Board Variants VME-HDMNTKIT Available Board AccessoriesVME-64GBSSDKIT SERIAL-MINI-D Serial Number Location Product Identification Hardware Preparation and Installation Requirements Hardware Preparation and InstallationUnpacking and Inspecting the Board Grms Environmental RequirementsEnvironmental Requirements Power Requirements Power Requirements Equipment Requirements Configuring the Board Rear Transition Module Installing Accessories 2 PMC/XMC Support Installation Procedure Installing and Removing the Board Hardware Preparation and Installation Completing the Installation Board Layout Controls, LEDs, and Connectors Front Panel Controls, LEDs, and Connectors Front Panel LEDs Reset SwitchLEDs Fail UserGENET1 TSEC1 Speed Onboard LEDs Status ConnectorsOnboard LEDs 1.1 RJ45 with Integrated Magnetics J1 Front Panel ConnectorsFront Panel Tri-Speed Ethernet Connector J1 Front Panel Serial Port J4 Front Panel Serial Port J4 VMEBus P1 Connector Controls, LEDs, and Connectors USB Connector J5USB Connector J5 VMEbus P1 Connector GND BR3 DS0 BR1 Lword GA2 Write BR2GA3 Dtack GA4 VMEbus P2 Connector Controls, LEDs, and Connectors VMEBus P2 Connector Flash Programming Header P7 Onboard ConnectorsFlash Program Connector P7 Custom Sata Connector J3 Sata Connector J3GND Sata Power Enable Sata TX + Sata Detect Sata RX 10 PMC J11 Connector PMC Connectors 11 PMC J12 Connector 12 PMC J13 Connector PAR64 GND CBE7 CBE6 CBE5 CBE4 13 PMC J14 Connector 14 Jtag Connector P6 Jtag Connector P6 GND Scan 2 TDI Scan 3 TMS Scan 3 TCK1 Scan 3 TDO GPO0 Scan 2 TMS Scan 2 TDO Scan 2 TCKScan 3 TCK GND Scan 4 TDI Scan 4 TCK Scan 4 Trst Scan 5 TMS Scan 5 TDO SD Connector J2 Controls, LEDs, and Connectors COP Connector P616 SD Connector J2 15 COP Header P10 17 XMC Connector XJ2 Pinout XMC Connector XJ2 18 P20x0 Debug Header Miscellaneous P2020 Debug Connectors Trigin MSRCID4 GND SwitchesGeographical Address Switch S1 GAP4 VME Scon SEL2GAP3 GAP2 SMT Configuration Switch S2 Bled MasterwpdisaGbemuxsel Plane Chipset Block DiagramFunctional Description Functional Description 1 e500 Processor CoreIntegrated Memory Controller Local Bus Controller LBC PCI Express InterfaceSecure Digital Hub Controller Sdhc 6 I2C Interface DMA Controller DuartEnhanced Three-Speed Ethernet Controller eTSEC General Purpose I/O Gpio 14 P20x0 Hardware Configuration Pins TimersSystem Memory Common On-Chip Processor COP Watchdog Timer Internal TimerFpga Tick Timer Ethernet Interfaces SPI Flash Programming SPI Bus InterfaceSPI Flash Memory Firmware Redundancy SPI Device Multiplexing Logic Front Uart Control Crisis Recovery PMC/XMC Sites Rear Uart Control XMC Add-on Card Sata InterfacePMC Add-on Card 12 USB VME Support13 I2C Devices 11.1 Tsi148 VME Controller Power Management Reset/Control FpgaOnboard Voltage Supply Requirement Voltage Supply Requirement Power Up Sequencing Requirements Clock Structure Reset Structure Reset Sequence Real-Time Clock BatteryThermal Management Thermal Interrupt Threshold Post Code Indicator on the LED Post Code IndicatorDebugging Support Jtag Chain and Board Rear Transition Module RTM Transition Module FeaturesCustom Debugging SBC Functional Description Physical Address Map Memory Maps and RegistersMemory Map Linux Devices Memory Map Flash Memory MapMemory Maps and Registers Flash Memory Map Linux Devices Memory Map PLD Revision Register Programmable Logic Device PLD RegistersPLD Year Register PLD Revision Register PLD Sequence Register PLD Month RegisterPLD Day Register PLD Power Good Monitor Register PLD Power Good Monitor RegisterWrgd RGD Pwrg Oper Reset Rsvd Pwrv PWRV1P2SWPWRG PLD LED Control Register10 PLD LED Control Register PMC1PN PLD PCI/PMC/XMC Monitor Register11 PLD PCI/PMC/XMC Monitor Register PLD Boot Bank Register PLD U-Boot and TSI Monitor Register12 PLD U-Boot and TSI Monitor Register 13 PLD Boot Bank Register Locka Bootb Boots PLD Write Protect and I2C Debug Register Wpdi WPN Ugen Flash Sabled Oper Reset14 PLD Write Protect and I2C Debug Register Rsvd Master Flash I2CDEB Serial I2CDEBUGEN=0 16 PLD Test Register PLD Test Register15 PLD Test Register 17 PLD GPIO2 Interrupt Register Rsvd NMI TICK0INT TICK1INT TICK2INT Oper ResetPLD GPIO2 Interrupt Register 18 PLD Shutdown and Reset Control and Reset Reason Register PLD Shutdown and Reset Control and Reset Reason RegisterCpureset Wdtime Lrsto Dnmask OUT Oper Reset 19 PLD Watchdog Timer Refresh Register PLD Watchdog Timer Refresh Register 21 PLD Watchdog Timer Count Register PLD Watchdog Timer Count RegisterPLD Watchdog Control Register 20 PLD Watchdog Control Register 22 Prescaler Register External Timer RegistersPrescaler Register Control Registers COC ENC Oper Reset23 Control Registers Ints Cint 25 Compare Low Word Registers Compare High and Low Word Registers24 Compare High Word Registers 27 Counter Low Word Registers Counter High and Low Word Registers26 Counter High Word Registers 102 Accessing U-Boot Boot System Boot System Boot OptionsBooting from a Network Booting from a USB Drive Booting from an Optional Sata Drive Booting VxWorks Through the Network Booting from an SD Card Analyzing Kernel Log Files after a Kernel Panic Using the Persistent Memory Feature MVME2500 Specific U-Boot Commands MVME2500 Specific U-Boot Commands Boot System Updating U-Boot Sf probe 112 Programming Model Reset ConfigurationPOR Configuration Settings Programming Model ETSEC3 Sgmmi TSEC1588ALARM Config Config Pins Selection Remarks ETSEC2 Sgmii LGPL1Ecmdc ETSEC1 TSEC1TXD0 TSEC1TXER Config Config Pins Selection Remarks Boot ROMLWE1/LBS1 TSEC2TXER MVME2500 Interrupt List Interrupt Controller Ethernet PHY Address I2C Bus Device AddressingI2C Bus Device Addressing PHY Types and MII Management Bus Address Mram Other Software ConsiderationsQuad Uart TSEC3 LBC Timing Parameters LBC Timing Parameters Clock Distribution Clock Distribution System Clock System Clock Local Bus Controller Clock Divisor Real Time Clock Input 124 Replacing the Battery Replacing the Battery Replacing the Battery Replacement Procedure 128 Related Documentation Emerson Network Power Embedded Computing Documents Table B-3 Related Specifications Related SpecificationsManufacturers’ Documents Related Documentation SATA-IO PCI-SIG 132 EMC Results pending testing Safety Notes Operation InstallationSafety Notes Cabling and Connectors Battery Sicherheitshinweise Sicherheitshinweise Betrieb 139 Batterie Kabel und Stecker Umweltschutz 142 Index Index Page HOW to Reach Literature and Technical Support