Emerson MVME2500 Programming Model, Overview, Reset Configuration, 1 POR Configuration Settings

Chapter 7

Programming Model

7.1Overview

This chapter includes additional programming information for the MVME2500.

7.2Reset Configuration

The MVME2500 supports the power-on reset (POR) pin sampling method for processor reset configuration. Each option and the corresponding default setting are described in the following table.

Table 7-1 POR Configuration Settings

	CONFIG	CONFIG PINS	CONFIG	SELECTION	REMARKS
1	CCB Config	LA[29:31]	000	41: CCB CLOCK-400 MHz
2	DDR PLL Config	TSEC_1588_CLK_O	001	8:1 DDR PLL-800 MHz	DDR rate is twice the
		UT			value of the DDR
		TSEC_1588_PULSE_			controller frequency,
					which is then divided by
		OUT1
					two through the
		TSEC_1588_PULSE_
					software.
		OUT2
3	Core 0 PLL	LBCTL, LALE	110	3:1 CORE CLOCK PLL	For 1200 MHz board
		LGPL2/LOE/LFRE		(1200 MHz)	configuration
			100	2:1 CORE CLOCK PLL (800	For 800 MHz board
				MHz)	configuration
4	Core 1 PLL	LWE0, UART_SOUT1	110	3:1 CORE CLOCK PLL	For 1200 MHz board
				(1200 MHz)	configuration
			100	2:1 CORE CLOCK PLL (800	For 800 MHz board
				MHz)	configuration
5	CPU Boot	LA27, LA16	10	e500 core 0 is allowed to
	Config			boot without waiting for
				configuration by an
				external master, while
				e500 core 1 is prevented
				from booting until
				configured by an external
				master or the other core.

MVME2500 Installation and Use (6806800L01H) 113